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71. 发明专利

JPH08125548A ENCODING CIRCUIT, DECODING CIRCUIT AND ENCODING/DECODING CIRCUIT FOR ERROR CORRECTION, AND DIGITAL DEVICE USING THE CIRCUITS 失效
公开(公告)号：JPH08125548A
公开(公告)日：1996-05-17
申请号：JP26211594
申请日：1994-10-26
申请人： HITACHI LTD
发明人： NAKASE JUNKO , UMEMOTO MASUO , SETOYAMA TORU
IPC分类号： G11B20/18 , H03M13/00 , H03M13/29 , H04L1/00
摘要： PURPOSE: To efficiently correct a burst shorter than the length of a C1 code by rearranging data with K continuous symbols of N-pieces of code words as one unit among the code words of the C1 code included in a product code after the product code is formed. CONSTITUTION: An error correction encoding circuit arranges recording information from a computer in a two-dimensional array (k1 symbols × k2 symbols) in a data arrangement means 31. A C2 encoding means 1 and a C1 encoding means 2 encode a C2 code and the C1 code. A data compositing means 3 rearranges data of a symbol unit. A data synthesis means 3 rearranges data in a symbol unit. A recording/reproducing system 4 records data encoded by the error correction encoding circuit into a recording medium. An error correction decoding circuit rearranges the series of data reproduced by the recording/ reproducing system 4 at the time of reproduction and reproduces it into the line of data on an original product code. Then, a C1 code decoding means 6 and a C2 code decoding means 7 decode the product code and transmit reproduced information to the computer.

72. 发明专利

JPH0738918A PICTURE SIGNAL SYNTHESIZER AND ITS METHOD 失效
公开(公告)号：JPH0738918A
公开(公告)日：1995-02-07
申请号：JP17879693
申请日：1993-07-20
申请人： HITACHI LTD
发明人： GUNJI HIROSHI , UMEMOTO MASUO , KIMURA JUNICHI , GONDA AKIKO
IPC分类号： H04N5/92 , G06T1/00 , G06T3/00 , G06T9/00 , H04N7/24 , H04N9/75 , H04N19/00
摘要： PURPOSE:To provide the picture synthesis processing unit or its method in which picture quality deterioration is suppressed even when compression coding is made in a system processing a picture. CONSTITUTION:When a picture in a frame memory 22 being a foreground is read while deviating its position in the insertion or chroma key processing, an address conversion circuit 40 sets the deviation of the position to be an integral multiple of the coding block size and the block positions at coding before and after synthesis processing are made to match with each other.

73. 发明专利

JPH06309793A DIGITAL SIGNAL RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH06309793A
公开(公告)日：1994-11-04
申请号：JP9408093
申请日：1993-04-21
申请人： HITACHI LTD
发明人： SAWAMURA HIDEHIKO , UMEMOTO MASUO , KUDO KOJI , ISHII HIROTAKE
IPC分类号： G11B5/09 , G11B20/10 , H03M5/00 , H04N5/92
摘要： PURPOSE:To obtain a digital data recording and reproducing device capable of adapting a quantization direct current regeneration even when a level fluctuation is generated at the time of a variable speed reproduction, etc. CONSTITUTION:The signal level of the digital data output of a discrimination circuit 507 is adjusted by a level adjusting circuit 508 by making the controlling signal of the level adjusting circuit 508 from the input signal of a quantization direct current regenerating circuit (not shown in the figures) with a level detecting circuit 505 and a control signal forming circuit 506. Thus, a equalized error due to the quantization direct current regenerating circuit is not generated even when the input signal is fluctuated. Consequently, identification mistakes are reduced by adapting the quantization direct current regenerating circuit at the time of the variable speed reproduction.

74. 发明专利

JPH05205407A DIGITAL SIGNAL MAGNETIC RECORDER 失效
公开(公告)号：JPH05205407A
公开(公告)日：1993-08-13
申请号：JP1172392
申请日：1992-01-27
申请人： HITACHI LTD
发明人： UMEMOTO MASUO
IPC分类号： G11B20/14 , H03M5/04 , H03M7/14
摘要： PURPOSE:To reduce the number of DC control bits by obtaining the total electric charge quantity of the current waveform of each digital signal block and compar ing it with the total electric charge quantity of the next block ahead to deter mine a 2-bit pattern. CONSTITUTION:A DC control 2-bit pattern inserting circuit 4 obtains a total electric charge quantity B of each digital signal block passing a 1-7 modulator 3 and compares an absolute value A(+) of A+B and an absolute value A(-) of A-B with each other in accordance with this quantity B and a total electric charge quantity A of the next block ahead. In the case of A(+) A(-), the last bit of the preceding block and the first bit of the current block are referred to insert connection pattern '01' or '10', thereby reducing the DC component of the digital signal. By this reduction method, the DC component of the digital signal is reduced by the small number of bits, namely, two bits. The DC component of the reproduced signal is reduced also by the same processing.

75. 发明专利

JPH0441869B2 失效
公开(公告)号：JPH0441869B2
公开(公告)日：1992-07-09
申请号：JP2624085
申请日：1985-02-15
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , MITA SEIICHI , NAGAHARA SHUSAKU , TANAKA SEIJI
IPC分类号： G11B5/52 , G11B5/027 , G11B20/02 , H04N9/80 , H04N9/82 , H04N9/83

76. 发明专利

JPH0413786B2 失效
公开(公告)号：JPH0413786B2
公开(公告)日：1992-03-10
申请号：JP3641582
申请日：1982-03-10
申请人： HITACHI LTD
发明人： TANAKA SEIJI , UMEMOTO MASUO , TAKAHASHI KENJI , NAGAHARA SHUSAKU , MITA SEIICHI
IPC分类号： H04N5/92 , G11B20/06

77. 发明专利

JPH0316435A MODULATION AND DEMODULATION SYSTEM FOR DIGITAL SIGNAL 失效
公开(公告)号：JPH0316435A
公开(公告)日：1991-01-24
申请号：JP14961389
申请日：1989-06-14
申请人： HITACHI LTD
发明人： UMEMOTO MASUO
IPC分类号： G11B20/14 , H03M5/12 , H03M5/14 , H03M7/46
摘要： PURPOSE:To reduce the generation of a DC component and to obtain the same aperture width as that of an NRZ code by combining 2 each of data and inverting the polarity between 1st half 2 0s and latter half 2 0s only when 4 consecutive 0s take place and at the boundary of bit intervals. CONSTITUTION:Input data AB, CD are inputted to a 4-bit shift register 3 via input terminals (1-1)-(1-4). The 4-bit shift register 3 fetches 4-phase input data A-D by using a clock E generated from a clock generating circuit 4 to generate a high speed serial data I. In order to detect whether or not data are all '0' at each of 4 units, an AND circuit 8a is used via inversion circuits (2-1)-(2-4) and when an output H goes to a high level, the inversion takes place at the boundary of data bits. Thus, the generation of DC component is reduced.

78. 发明专利

JPS62246175A SCRAMBLING CIRCUIT 失效
公开(公告)号：JPS62246175A
公开(公告)日：1987-10-27
申请号：JP8802386
申请日：1986-04-18
申请人： HITACHI ELECTRONICS , HITACHI LTD
发明人： OKIGUCHI KOTARO , UMEMOTO MASUO , ETO YOSHIZUMI
IPC分类号： G11B20/12
摘要： PURPOSE:To easily monitor data even if blocks are transposed, by operating random numbers different by blocks in parity parts and detecting the malfunction of a time base corrector with detection omission probability 1/2n because random numbers of different blocks are applied to error detection parity and operating the same random numbers for individual block in data parts. CONSTITUTION:If a control signal phi1 is loaded for every error detection block, the signal phi1 is applied to a counter 18, and the loaded address is applied to a ROM 19 and a signal is obtained where random numbers different by blocks are operated in only parity parts by a control signal phi2 and the same random numbers for individual blocks are operated in the other parts. Consequently, even if a time base skip signal for variable speed reproducing or the like is inputted, error detection is possible because random numbers corresponding to a prescribed address are applied again in the skip position. Even if the time base is transposed in block units, data parts are correctly restored because random numbers for data parts are equal in individual blocks.

79. 发明专利

JPS62192075A AUTOMATIC EQUALIZING METHOD AND DEVICE IN DIGITAL RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPS62192075A
公开(公告)日：1987-08-22
申请号：JP3279386
申请日：1986-02-19
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： UMEMOTO MASUO , ETO YOSHIZUMI , TAKESHITA KAZUYUKI
IPC分类号： G11B20/10 , H04N5/92
摘要： PURPOSE:To automatically obtain an optimum characteristic with good accuracy by changing the characteristic of a variable equalizer so that the number of an output signal to pass through the vicinity of the center of the eye pattern of the output signal of the variable equalizer can be minimized. CONSTITUTION:The first variable equalizer 100 equalizes the reproducing signal of a recorded digital signal, outputs it to the circuit at the rear step, and the second variable equalizer 101 also has the same characteristic as the equalizer 100. The first means 102 counts the number of the output signal to pass through in a prescribed time in a prescribed scope from the central value in the identifying point of the eye pattern of the reproducing signal by the equalizer 101. The second means 103 changes the characteristic of the equalizer 101 periodically for a prescribed time, detects the characteristic when the counting value of the means 102 comes to be minimum and sets the characteristic of the equalizer 100 by matching with the characteristic.

80. 发明专利

JPS62188411A GAIN CONTROL CIRCUIT 失效
公开(公告)号：JPS62188411A
公开(公告)日：1987-08-18
申请号：JP2882786
申请日：1986-02-14
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： SAWAMURA HIDEHIKO , TAKESHITA KAZUYUKI , KATAYAMA HITOSHI , ETO YOSHIZUMI , UMEMOTO MASUO
IPC分类号： H04N5/14 , H03G3/12
摘要： PURPOSE:To control the gain without changing an emitter bias current by causing a constant current to flow dividedly to a current path including a variable resistive element and the other current path by means of a differential circuit and connecting two kinds of current paths to the emitter. CONSTITUTION:A common emitter amplifier circuit consists of a transistor (TR) 1, a variable resistive element 5, and a resistor 7. The DC bias component in the emitter current of the TR 1 is divided differentially by TRs 2, 3 and the emitter current is decided by a TR 4. The input signal is amplified by the TR 1 and the signal component is blocked by an inductance 6 at the emitter side of the TR 1, then the gain depends on a ratio of a collector resistor 7 to an AC resistance of the variable resistor element 5. The DC bias current flowing to the TR 1 being the sum of currents flowing to the TRs 2, 3 is set by resistors 12-14 of the TR 4 by changing a DC bias current flowing to the variable resistive element 5 by means of the control voltage.

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