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71. 发明专利

JPH01121964A INTEGRATED CIRCUIT 失效
公开(公告)号：JPH01121964A
公开(公告)日：1989-05-15
申请号：JP27921687
申请日：1987-11-06
申请人： HITACHI LTD
发明人： OKADA YUTAKA , MATSUMOTO YOSHIYUKI
IPC分类号： G06F13/38
摘要： PURPOSE:To reduce the number of control signals and to simplify a control circuit by providing a D FF and inputting the control signal from the external through a pointing pad to set the input/output mode. CONSTITUTION:When a reset terminal R of a D FF 1 for input/output information storage is set to the H level, the input/output set mode is set, and the Q output goes to the L level, and an enable terminal EN of a non-inverting ternary output buffer 4 goes to the L level and its output is open. Then, the control signal is inputted from the external to an inverting input buffer 2 through a pointing pad 5. If the L level is inputted from the external, the terminal Q goes to the H level because the H level is inputted to the terminal D when a clock pulse is inputted after return of a reset signal to the L level. As the result, the buffer 4 is made conductive and a ternary inverter 3 is cut off to set the output mode. If the H level is inputted from the external, the Q terminal goes to the L level and the input mode is set. Thus, the number of control signals is reduced to simplify the control circuit.

72. 发明专利

JPS6413804A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS6413804A
公开(公告)日：1989-01-18
申请号：JP16857087
申请日：1987-07-08
申请人： HITACHI LTD
发明人： OKADA YUTAKA , WATABE TOMOYUKI , TANAKA SATOSHI
IPC分类号： H03M1/66 , H03H17/00
摘要： PURPOSE:To reduce harmonic component of an output signal of a D/A converter by using an output signal of a D/A converter so as to apply amplitude modulation to a signal phase-synchronized with a timing when the output of the D/A converter varies stepwise and demodulating the result. CONSTITUTION:A stepwise analog signal outputted from a D/A converter 2 operated by a prescribed clock is given to a balance modulator 3, where a carrier signal composed sinusoidal waves obtained from the clock through the processing by a low pass filter 10 is subjected to carrier suppression amplitude modulation by the analog signal. In this case, when the analog signal changes stepwise, since the phase-synchronizing signal is subjected to amplitude modulation so as to make the output of the modulator 3 zero, the output of the modulator 3 cahanges continuously. Then the output of the modulator 3 is subjected to synchronization detection by using the carrier signal at a synchronization detector 7 to obtain a smooth analog signal and the residual harmonic component of the analog signal is eliminated by a low pass filter 8.

73. 发明专利

JPS61208260A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61208260A
公开(公告)日：1986-09-16
申请号：JP4829085
申请日：1985-03-13
申请人： HITACHI LTD
发明人： OKADA YUTAKA , WASHIO KATSUYOSHI , WATABE TOMOYUKI , OKABE TAKAHIRO
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8222 , H01L29/08 , H01L29/73 , H01L29/732
摘要： PURPOSE:To prevent the generation of a latch-up by a method wherein an N buried layer just under a base layer is omitted, withstanding voltage is increased while forming an N buried layer just under a section in the vicinity of the base layer, collector series resistance is reduced and a Schottky diode is added. CONSTITUTION:An N buried layer is not shaped just under a base layer 6, N buried layers 2 are formed to the periphery sections of the base layer, high concentration layers 10 reaching the buried layers 2 are shaped, and collector resistance is lowered. Consequently, withstanding voltage between a base and a collector is increased while collector series resistance is reduced. A Schottky diode is formed by metallic electrodes 13, 14 and low-concentration N-type layers 3b in order to eliminate the effect (a latch-up- of a parasitic transistor constituted by the P-type region (an emitter) 6, the N-type epitaxial layers (bases) 3b and a substrate (a collector) 1.

74. 发明专利

JPS6060760A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6060760A
公开(公告)日：1985-04-08
申请号：JP16817283
申请日：1983-09-14
申请人： HITACHI LTD
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/74 , H01L21/331 , H01L21/8226 , H01L27/082 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To increase withstanding voltage and reduce collector series resistance by omitting an N layer just under a base while forming an N buried layer just under at least one part of the periphery of a base layer in a bipolar transistor. CONSTITUTION:An N type epitaxial layer 3 and an N type region 10 are formed on a semiconductor substrate 1, the layer 3 and region 10 are used as collector regions while a P type base region 6 is shaped in the region 3, and an N type emitter region 9 is formed in the base region 6, thus constituting a bipolar transistor. In the transistor constituted in this manner, an N buried layer 2 is shaped just under the periphery of the base layer 6, and is not formed just under the base layer 6. Accordingly, the transistor having high withstanding voltage can be formed on the thin epitaxial layer. Collector resistance can be reduced.

75. 发明专利

JPS6020534A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6020534A
公开(公告)日：1985-02-01
申请号：JP12767583
申请日：1983-07-15
申请人： HITACHI LTD
发明人： YAMAZAKI KOUICHI , OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To perform the microminiaturization of an element and the lowering of the resistance of a wiring compatible by doping arsenic to polycrystalline silicon on an emitter in a transistor and doping either of arsenic and phosphorus or only phosphorus to polycrystalline silicon for the wiring except a section on the emitter through a self-alignment method. CONSTITUTION:A polycrystalline silicon layer 8 is formed in such a manner that non-doped polycrystalline silicon is deposited and arsenic is doped through the implantation of arsenic or polycrystalline silicon to which arsenic is doped is used. Phosphorus is diffused to the polycrystalline silicon 8 from phosphorus glass 21 through heat treatment, phosphorus is doped to the polycrystalline silicon, and polycrystalline silicon layers 8' to which phosphorus is doped are formed. Phosphorus is not doped to an emitter and the polycrystalline silicon on collector withdrawal regions 6, 7 at that time, phosphorus is not doped to an emitter region, and phosphorus can be doped to the polycrystalline silicon except a section on the emitter region in a self-alignment manner. The polycrystalline silicon is patterned, a protective oxide film 10 is shaped, and a base metallic electrode 9 is formed, thus forming a transistor.

76. 发明专利

JPS5989454A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5989454A
公开(公告)日：1984-05-23
申请号：JP19891682
申请日：1982-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA YUTAKA , KANEKO KENJI , OKABE TAKAHIRO , NAGATA MINORU , YAMAZAKI KOUICHI , MATSUMOTO KEIZOU
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L29/73 , H03K19/091
摘要： PURPOSE:To reduce delay time for the transmission of signals in a laminated I L by using a current mirror system in order to rapidly extinguish stored charges in a transistor (Tr). CONSTITUTION:A power supply 1, an injector 2 and a common emitter 3 are set up to an upper-layer I L circuit block A. The injector line 3 and a common emitter 4 are set up to a lower-layer I L circuit block B. Q0 represents the N-P-N Tr of an I L gate, and Q2 represents an N-P-N Tr constituting the interface of the laminated I L. Q3 and Q4 constitute a current mirror circuit. A period while Q3 is turned OFF is shortened because the base currents are small and stored charges are little.

77. 发明专利

JPS5984463A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS5984463A
公开(公告)日：1984-05-16
申请号：JP19341082
申请日：1982-11-05
申请人： HITACHI LTD
发明人： KANEKO KENJI , OKADA YUTAKA , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU , OGURA SADAO , KUDOU SATOSHI
IPC分类号： H01L27/082 , H01L21/331 , H01L21/768 , H01L21/8226 , H01L23/522 , H01L27/08 , H01L29/73
摘要： PURPOSE:To prevent the short circuit between the base and the emitter and reduce the base resistance by a method wherein the distance between an emitter diffusion hole and the side wall of an emitter lead-out poly Si layer is determined by using a mask, while the poly Si layer is covered with an SiO2 film, the SiO2 film of a base layer is removed by self-alignment method, and a metallic base terminal is laid. CONSTITUTION:The P-base 204 is provided at a region wherein an n type Si collector layer 203 is isolated by oxide films 209, an n emitter layer 205 is formed by providing an aperture through an SiO2 thin film 208, and a poly Si 206 and an SiO2 207 are superposed. The Si 206 is made larger than the emitter diffusion hole, and the eaves of the SiO2 film 207 is formed and patterned, thus providing an SiO2 210 on the side wall and then being covered with an Si3N4 211. The film 211 at the stepwise difference is removed by adhering a metal 212. An SiO2 214 is thickly formed on the wall on the poly Si side by removing the metallic film 212. The Si3N4 211 is removed, only a thin SiO2 208 is removed, and a base electrode of a metal 215 is attached. This constitution enables to largely reduce the base resistance while the short circuit between the base and the emitter is prevented.

78. 发明专利

JPS5980967A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5980967A
公开(公告)日：1984-05-10
申请号：JP19086482
申请日：1982-11-01
申请人： HITACHI LTD
发明人： OKADA YUTAKA , KANEKO KENJI , YAMAZAKI KOUICHI , OKABE TAKAHIRO , NAGATA MINORU
IPC分类号： H01L21/76 , H01L21/331 , H01L29/72 , H01L29/73
摘要： PURPOSE:To eliminate the trouble pertaining to the leak current generating between an emitter and a collector as well as to enable to markedly reduce the measurements of an element including the circumferential part by a method wherein a high density impurity layer is provided at the part where an emitter region comes in contact with an oxide film. CONSTITUTION:A P type impurity region 13 is formed using a nitride film as a mask by performing a selective etching on the nitride film and then performing another etching on an oxide film. The P type impurity region 13 is left on the region located below the circumferential part of a nitride film 102 by etching the silicon of the part which is not covered by the nitride film, and the P type impurity region of the part which is not covered by a nitride film 102 is removed. A P type region 13 is formed by performing an oxidation on the circumference of the region, which will be turned to the active area of a transistor, is formed by providing a thick oxide film 10 on the part which is not covered by the nitride film. Then, an emitter region 5 and a collector region 6 are formed by diffusing N type impurities on a single crystal silicon from a polycrystalline film 103, and an oxide film 104 is formed on the surface thereof.

79. 发明专利

JPS5574179A SEMICONDUCTOR NONNVOLATILE MEMORY 失效
公开(公告)号：JPS5574179A
公开(公告)日：1980-06-04
申请号：JP14648678
申请日：1978-11-29
申请人： HITACHI LTD
发明人： WATANABE TOMOYUKI , KANEKO KENJI , NAKAMURA TOORU , OKADA YUTAKA , OKABE TAKAHIRO , NAGATA JIYOU , ITOU YOUKICHI , TORIYABE TATSU
IPC分类号： H01L27/112 , G11C11/411 , G11C11/412 , G11C14/00 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PURPOSE:To provide an I L with non-volatile memory function by forming a p- type control layer close to the base layer of NPN-transistor of I L and further providing a floating gate through an insulator film on the substrate surface between the both layers. CONSTITUTION:A floating gate 23 is provided through an insulator film 22 between the base layer 15 and the control layer 21 in an NPN-transistor. The layer 14 consisting of word line is p-type isolation layer and common with I L in the direction of word line. When no electrons are present in the gate 23, it functions as normal I L. The presence of electrons in the gate 23 allows channel to be formed in n-layer 25, holes to be flowed from p-layer 13 to p-layer 21, and the base current to reduce thereby reducing the collector 16 current. This allows the amount of electron accumulated in the gate 23 to be detected as the change in the collector current, enabling memory operation. To perform writing, pn-junction of the layers 21 and 14 are subject to breakdown to allow electron injection. For reading, designated word line is made to zero potential and other word lines to a high level. To erase the memory, ultraviolet ray is irradiated on the element.

80. 发明专利

JPS52133758A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS52133758A
公开(公告)日：1977-11-09
申请号：JP4994876
申请日：1976-05-04
申请人： HITACHI LTD
发明人： TSUKADA TOSHIROU , OKABE TAKAHIRO , WATANABE TOMOYUKI , KANEKO KENJI , OKADA YUTAKA
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L27/02 , H01L29/73
摘要： PURPOSE:To produce a high-speed, high-performance I L circuit element by using a PNP forward transistor and an NPN forward transistor in place of the lateral PNP transistor and NPN reverse transistor of the I L.

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