会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 71. 发明专利
    • FORMATION OF WIRING
    • JPS60183738A
    • 1985-09-19
    • JP3851884
    • 1984-03-02
    • HITACHI LTD
    • KASAHARA OSAMU
    • H01L21/3213H01L21/88
    • PURPOSE:To improve the yield by a method in which conductive metal films are formed to be adhered on a substrate provided with patterns of non-wiring sections, the whole surface thereof is coated with a mask member and etch-packed, and the conductive metal films are etched away. CONSTITUTION:Patterns of non-wiring sections 3 are formed on a substrate 1 applied with an insulation film 2. Al alloy films 5 are formed to be adhered on the non-wire section patterns 3 and on the substrate. A mask member 6 is then applied thereon, and wholly etched so as to expose the Al alloy films 5a. The Al alloy films 5a are then etched by a wet etching method, If the non-wiring section patterns 3 are composed of an insulative material while the mask member 6 is also insulative, the mask material 6 may be used as an interlaminar insulative material instead of removing and applied to multiplayer wiring. If both of the non-wiring section patterns 3 and the mask member 6 are photoresist, they are etched by O2 plasma etching to form wiring patterns with an Al alloy film 5b. In such a manner, it is prevented that scraps of fragments of conductive metal film or metal film are adhered to conductive metal films of wiring pattarns, and accordingly short-circuit can be prevented.
    • 73. 发明专利
    • Film forming device
    • 电影制作装置
    • JPS59208068A
    • 1984-11-26
    • JP8273483
    • 1983-05-13
    • Hitachi LtdHitachi Micro Comput Eng Ltd
    • KASAHARA OSAMUTAKAHASHI SUU
    • C23C14/24C23C14/34H01L21/203H01L21/285
    • C23C14/24
    • PURPOSE:To improve covering performance in the stepped part of a base layer and to realize lift-off by disposing guides between wafers and a film material source for generating film particles. CONSTITUTION:The inside of a bell jar 11 is set at a prescribed degree of vacuum and the inside as well as wafers 14 and, for example, Al 15 on an evaporating tray 17 are heated by a heating means 18. Then the particles of the Al 15 scatter toward four ways in the bell-jar 11 with a scattering source 16 as a center. A part of the particles arrives at the surface of the wafers 14 and forms an Al film thereon. Guide cylinders 19 are disposed between the wafers and the source, the Al particles arrive at the wafers 14 only from the perpendicular direction thereof. Therefore if the wafers 14 are moved relatively with the cylinders 19 by operating a wafer supporting part 13, the films deposited with the Al respectively in the perpendicular direction are formed over the entire surface of the wafers 14.
    • 目的:提高基层阶梯部分的覆盖性能,并通过在晶片和薄膜材料源之间设置引导件来实现剥离,从而产生膜颗粒。 构成:钟罩11的内部被设定在规定的真空度,并且内部以及蒸发托盘17上的晶片14和例如Al 15被加热装置18加热。然后, Al 15以喇叭口11以散射光源16为中心向四个方向散射。 一部分颗粒到达晶片14的表面并在其上形成Al膜。 引导圆筒19设置在晶片和源之间,Al颗粒仅从其垂直方向到达晶片14。 因此,如果晶片14通过操作晶片支撑部分13而相对于气缸19移动,则在晶片14的整个表面上形成分别垂直方向沉积的Al的膜。
    • 74. 发明专利
    • Semiconductor integrated circuit device and manufacture thereof
    • 半导体集成电路器件及其制造
    • JPS5780739A
    • 1982-05-20
    • JP15594580
    • 1980-11-07
    • Hitachi Ltd
    • KASAHARA OSAMUSHIMIZU SHINJIMIYAZAWA HIROYUKINAKADA KENSUKE
    • H01L29/78H01L21/3205H01L23/52H01L23/532H01L27/108
    • H01L27/10805H01L23/53257H01L23/53271H01L2924/0002H01L2924/00
    • PURPOSE:To obtain a wire which can match by itself and has small specific resistance and fast signal transmission speed with heat resistance for an IC by forming in 3-layer structure of high melting point metal-metal containing polysilicon-Si. CONSTITUTION:A gate electrode of 3-layer structure is formed on the gate oxidized film 53 of a P type Si substrate 51, N type layers 572, 573 matched by itself are provided, the 3-layer structure electrode is attached to the layer 572, and an aluminum layer is attached to the N type layer 573. To form the electrode of 3-layer structure, CVD polysilicons 541, 542 are formed, phosphorus is added, Mos 551, 552 containing 10wt% of Si are commonly deposited and laminated, pure Mos 561, 562 are sputtered and laminated, are then plasma etched to form the electrode of 3-layer, the electrode is then annealed in N2, and Si is uniformly distributed in the Mo layer. According to this structure, the three layers are bonded to each other, with the result that the specific resistance becomes vary small value such as 30-35muOMEGAcm. Further, the Mo containing Si prevents an impurity to be mixed at the depositing time from being stopped by the polysilicon and not to be diffused in a semiconductor substrate. In this manner, a semiconductor integrated circuit device having small specific resistance and short transmission time can be obtained.
    • 目的:通过在含有多晶硅的高熔点金属 - 金属的3层结构中形成,获得能够自己匹配的电线,具有小的电阻率和具有耐热性的IC的耐热性的快速信号传输速度。 构成:在P型Si衬底51的栅极氧化膜53上形成3层结构的栅电极,设置与其自身匹配的N +型层572,573,将3层结构电极附着于 层572和铝层附着到N +型层573.为了形成3层结构的电极,形成CVD多晶硅541,542,加入磷,含有10重量%的氧化物的Mos 551,552 通常沉积和层压Si,纯Mos 561,562被溅射和层压,然后进行等离子体蚀刻以形成3层电极,然后将电极在N 2中退火,并且Si均匀地分布在Mo层中。 根据该结构,三层结合,结果电阻率变小,例如30-35μmOMEGAcm。 此外,含Mo的Si防止杂质在沉积时间被多晶硅停止而不被扩散到半导体衬底中。 以这种方式,可以获得具有小电阻和短的传输时间的半导体集成电路器件。