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71. 发明授权

US07990228B2 Semiconductor device and wiring part thereof 有权
标题翻译：半导体器件及其布线部分
公开(公告)号：US07990228B2
公开(公告)日：2011-08-02
申请号：US12060941
申请日：2008-04-02
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
IPC分类号： H04B3/28
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/111 , H05K2201/0175 , H05K2201/0179 , H05K2201/09763 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H01L2924/00
摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.
摘要翻译：提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。第一金属电极板和第二金属电极板之间插入厚度等于或小于1μm的电介质膜。

72. 发明授权

US07889584B2 Semiconductor memory device having input first-stage circuit 有权
标题翻译：具有输入第一级电路的半导体存储器件
公开(公告)号：US07889584B2
公开(公告)日：2011-02-15
申请号：US11580275
申请日：2006-10-13
申请人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
发明人： Yoji Idei , Susumu Hatano , Yoji Nishio , Seiji Funaba , Yutaka Uematsu
IPC分类号： G11C7/02
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.
摘要翻译：本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

73. 发明授权

US07856072B2 Semiconductor device, memory device and memory module having digital interface 有权
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US07856072B2
公开(公告)日：2010-12-21
申请号：US12481798
申请日：2009-06-10
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00 , H03B1/00 , G05F1/10
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

74. 发明授权

US07852145B2 Semiconductor device having power supply system 有权
标题翻译：具有电源系统的半导体装置
公开(公告)号：US07852145B2
公开(公告)日：2010-12-14
申请号：US12320367
申请日：2009-01-23
申请人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
发明人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
IPC分类号： G05F1/10
CPC分类号： H01L23/50 , G06F1/26 , H01L2224/16225 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.
摘要翻译：提供一种半导体器件，包括：第一半导体集成电路; 接地线和电源线槽，其向第一半导体集成电路供电; 以及连接在地线和电源线之间的可变阻抗分量。

75. 发明授权

US07725778B2 Semiconductor integrated circuit and electronic device 有权
标题翻译：半导体集成电路和电子设备
公开(公告)号：US07725778B2
公开(公告)日：2010-05-25
申请号：US12314291
申请日：2008-12-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11B20/20 , G11C29/00 , G01R31/26
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.
摘要翻译：虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且由测量电路获得的延迟时间用于确定输出电路的信号转换时间。信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。以这种方式，实现了由最近端的反射点减轻反射的信号传输。

76. 发明授权

US07689944B2 Method for designing semiconductor apparatus, system for aiding to design semiconductor apparatus, computer program product therefor and semiconductor package 失效
标题翻译：半导体装置的设计方法，辅助设计半导体装置的系统，其计算机程序产品和半导体封装
公开(公告)号：US07689944B2
公开(公告)日：2010-03-30
申请号：US11511438
申请日：2006-08-29
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Satoshi Isa , Yoji Nishio , Seiji Funaba , Yukitoshi Hirose
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5068 , H01L2224/05553 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K1/0231 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.
摘要翻译：公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。决定设计指南来解决确定的问题部分。

77. 发明授权

US07633147B2 Semiconductor unit having two device terminals for every one input/output signal 失效
标题翻译：半导体单元具有用于每一个输入/输出信号的两个器件端子
公开(公告)号：US07633147B2
公开(公告)日：2009-12-15
申请号：US10672551
申请日：2003-09-26
申请人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
发明人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
IPC分类号： H01L23/538
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.
摘要翻译：构成存储器件的半导体单元具有存储芯片，具有三个布线层的封装基板。电源表面（VDD表面）和（GND表面）被布线在封装衬底上，而封装内的DQ总线布线在两个电源表面之间的中间层上。存储器件每一个封装内DQ总线具有两个DQ引脚。封装内的DQ总线通过通孔连接到存储器芯片的信号端子焊盘。鉴于两个DW引脚，用于将封装内DQ DQ总线与信号端子焊盘连接的通孔构成分支线。

78. 发明申请

US20090195295A1 Semiconductor device having power supply system 有权
标题翻译：具有电源系统的半导体装置
公开(公告)号：US20090195295A1
公开(公告)日：2009-08-06
申请号：US12320367
申请日：2009-01-23
申请人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
发明人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
IPC分类号： G11C5/14
CPC分类号： H01L23/50 , G06F1/26 , H01L2224/16225 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.
摘要翻译：提供一种半导体器件，包括：第一半导体集成电路; 接地线和电源线槽，其向第一半导体集成电路供电; 以及连接在地线和电源线之间的可变阻抗分量。

79. 发明申请

US20090189293A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090189293A1
公开(公告)日：2009-07-30
申请号：US12318700
申请日：2009-01-06
申请人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
发明人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01055 , H01L2924/15311 , H01L2224/05599
摘要： A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.
摘要翻译：具有片上芯片结构的半导体器件由第一半导体芯片和偶数对的第二半导体芯片组成，所有第二半导体芯片在中介层的表面上层压在一起。第一半导体芯片控制每对第二半导体芯片，以激活一个第二半导体芯片，同时使另一个第二半导体芯片失效。第二半导体芯片以通孔和电极通过凸块彼此相对定位的方式配对在一起。由于提供有驱动电压（VDD）的驱动电压电极和提供参考电位（VSS）的参考电位电极在成对的第二半导体芯片之间相互连接在一起，因此可以增加每个第二半导体芯片的总静电电容以便在不增加半导体器件的整体布局面积的情况下显着降低馈送噪声。

80. 发明授权

US07447038B2 Module 有权
标题翻译：模块
公开(公告)号：US07447038B2
公开(公告)日：2008-11-04
申请号：US11304625
申请日：2005-12-16
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： H05K1/00
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
摘要翻译：在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

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