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71. 发明授权

US07682942B2 Method for reducing pillar structure dimensions of a semiconductor device 有权
标题翻译：减少半导体器件的柱结构尺寸的方法
公开(公告)号：US07682942B2
公开(公告)日：2010-03-23
申请号：US11864205
申请日：2007-09-28
申请人： Yung-Tin Chen , Michael Chan , Paul Poon , Steven J. Radigan
发明人： Yung-Tin Chen , Michael Chan , Paul Poon , Steven J. Radigan
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/0274 , G03F7/40
摘要： A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist.
摘要翻译：一种方法在半导体晶片上形成柱结构，并且包括提供半导体层的步骤。一层光致抗蚀剂被施加在半导体层上。光致抗蚀剂层用初始图案曝光以实现光致抗蚀剂层。然后蚀刻掉光致抗蚀剂层以提供光致抗蚀剂图案以产生柱结构。在曝光光致抗蚀剂层的步骤之前和蚀刻步骤之前，在光致抗蚀剂层中处理光致抗蚀剂图案，以减小光致抗蚀剂层中的光刻胶图案的尺寸。

72. 发明申请

US20090321789A1 Triangle two dimensional complementary patterning of pillars 有权
标题翻译：支柱三角形二维互补图案化
公开(公告)号：US20090321789A1
公开(公告)日：2009-12-31
申请号：US12216109
申请日：2008-06-30
申请人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
发明人： Chun-Ming Wang , Yung-Tin Chen , Roy E. Scheuerlein
IPC分类号： H01L21/822 , H01L27/10
CPC分类号： H01L27/101 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物，用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。每三个相邻的柱形成等边三角形，每个柱包括半导体器件。多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

73. 发明授权

US07553611B2 Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure 有权
标题翻译：掩盖重复的覆盖和对准标记，以允许在垂直结构中重复使用光掩模
公开(公告)号：US07553611B2
公开(公告)日：2009-06-30
申请号：US11097496
申请日：2005-03-31
申请人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
发明人： Yung-Tin Chen , Christopher J Petti , Steven J Radigan , Tanmay Kumar
IPC分类号： G03C5/00 , G03C1/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.
摘要翻译：在形成单片三维存储器阵列时，可以使用光掩模多于一次。重新使用光掩模创建步进器使用的第二，第三或更多个参考标记实例，以实现对齐（对齐标记）并且直接在相同参考标记的先前实例之上测量对齐（覆盖标记）。相同参考标记的先前实例可能引起对参考标记的当前实例的干扰，使对准和测量复杂化。使用本发明的方法，垂直插入相同参考标记的后续实例之间的阻挡结构，以防止干扰。

74. 发明授权

US07494765B2 Method for patterning photoresist pillars using a photomask having a plurality of chromeless nonprinting phase shifting windows 有权
标题翻译：使用具有多个无色非印刷相移窗的光掩模图案化光刻胶柱的方法
公开(公告)号：US07494765B2
公开(公告)日：2009-02-24
申请号：US11559620
申请日：2006-11-14
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G03F7/20 , G03F7/40
CPC分类号： G03F1/34 , G03F1/36
摘要： A method for patterning a photoresist using a photomask to form an integrated circuit, the photomask including a first area transmitting light in a first phase surrounded by a second area, the second area transmitting light in a second phase, the second phase opposite the first phase. No blocking material separates the first area from the second area. After development of the photoresist, the transition along a perimeter between the first and the second area causes formation of a residual photoresist feature on the photoresist surface due to phase canceling of light. If the first area is small enough, it is nonprinting, i.e., the opposite sides of the residual photoresist feature formed at its perimeter merge, forming a contiguous photoresist feature, such as a pillar, and thus a corresponding patterned feature or pillar after etching (e.g., to form a portion of a memory cell, etc.).
摘要翻译：一种使用光掩模图案化光致抗蚀剂以形成集成电路的方法，所述光掩模包括第一区域，所述第一区域以由第二区域包围的第一相位的方式透射光，所述第二区域在第二相位中透射光，所述第二相位与所述第一相位相反。没有阻挡材料将第一区域与第二区域分开。在光致抗蚀剂显影之后，沿着第一和第二区域之间的周边的过渡会导致由于光的相位消除而在光致抗蚀剂表面上形成残留光致抗蚀剂特征。如果第一区域足够小，则它是非打印的，即，在其周边处形成的剩余光致抗蚀剂特征的相对侧合并，形成连续的光致抗蚀剂特征，例如柱，因此蚀刻后相应的图案化特征或柱（例如，形成存储单元的一部分等）。

75. 发明申请

US20090004880A1 MASK REUSE IN SEMICONDUCTOR PROCESSING 有权
标题翻译：半导体处理中的掩蔽重现
公开(公告)号：US20090004880A1
公开(公告)日：2009-01-01
申请号：US11772137
申请日：2007-06-30
申请人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
发明人： Calvin K. Li , Yung-Tin Chen , En-Hsing Chen , Paul Wai Kie Poon
IPC分类号： H01L21/32
CPC分类号： H01L21/32139 , G03F1/42 , G03F7/70633 , G03F9/7076 , H01L23/544 , H01L27/101 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A mask is reused to form the same pattern in multiple layers in semiconductor processing. Reference marks that allow alignment accuracy to be checked are also formed with the mask. The manner of using the mask advantageously mitigates interference between reference marks in different layers.
摘要翻译：在半导体处理中，掩模被重复使用以在多层中形成相同的图案。也可以使用掩模形成允许校准精度的参考标记。使用掩模的方式有利地减轻不同层中的参考标记之间的干扰。

76. 发明授权

US07172840B2 Photomask features with interior nonprinting window using alternating phase shifting 有权
标题翻译：光掩模功能与内部非打印窗口使用交替相移
公开(公告)号：US07172840B2
公开(公告)日：2007-02-06
申请号：US10728436
申请日：2003-12-05
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： G01F9/00 , G03C5/00
CPC分类号： G03F1/30
摘要： Aspects of the present invention provide for a novel photomask for patterning features for an integrated circuit, the photomask including masked features having interior nonprinting windows. In some embodiments, the interior nonprinting window is an alternating phase shifter, while the area surrounding the masked features transmits light unshifted. In other embodiments, the interior nonprinting window transmits light unshifted, while the area surrounding the masked features is an alternating phase shifter. Thus any arrangement of features can be patterned with no phase conflict.
摘要翻译：本发明的方面提供了一种用于集成电路的图形化特征的新型光掩模，该光掩模包括具有内部非印刷窗口的掩蔽特征。在一些实施例中，内部非打印窗口是交替移相器，而围绕被掩蔽的特征的区域透射未被移动的光。在其他实施例中，内部非打印窗口透射未被移动的光，而围绕屏蔽特征的区域是交替移相器。因此，可以对任何特征的布置进行图案化而没有相位冲突。

77. 发明申请

US20210020659A1 Three-Dimensional Ferroelectric Random-Access Memory (FeRAM) 有权
公开(公告)号：US20210020659A1
公开(公告)日：2021-01-21
申请号：US17039746
申请日：2020-09-30
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L27/11597 , G11C11/22 , H01L27/11587
摘要： A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

78. 发明申请

US20130094278A1 Non-Volatile Memory Cell Containing an In-Cell Resistor 有权
标题翻译：含有单元电阻的非易失性存储单元
公开(公告)号：US20130094278A1
公开(公告)日：2013-04-18
申请号：US13552355
申请日：2012-07-18
申请人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
发明人： Kun Hou , Yung-Tin Chen , Zhida Lan , Huiwen Xu
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.
摘要翻译：非易失性存储单元包括与转向元件串联设置的第一电极，操舵元件，金属氧化物存储元件，与转向元件和金属氧化物存储元件串联的介质电阻器和第二电极。

79. 发明授权

US08357606B2 Resist feature and removable spacer pitch doubling patterning method for pillar structures 有权
标题翻译：支柱结构的抗蚀特征和可移除的间隔物间距倍增图案化方法
公开(公告)号：US08357606B2
公开(公告)日：2013-01-22
申请号：US13331267
申请日：2011-12-20
申请人： Yung-Tin Chen , Steven J. Radigan
发明人： Yung-Tin Chen , Steven J. Radigan
IPC分类号： H01L21/44
CPC分类号： H01L45/1691 , H01L21/0337 , H01L21/0338 , H01L27/1021
摘要： A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成层，在该层上形成可成像材料的多个间隔特征，在多个特征上形成侧壁间隔物，并填充第一特征上的第一侧壁间隔物之间的空间以及具有填充特征的第二特征上的第二侧壁间隔物。该方法还包括去除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且使用第一特征，填充物特征和第二特征作为掩模来蚀刻层。

80. 发明授权

US08084682B2 Multiple band gapped cadmium telluride photovoltaic devices and process for making the same 失效
标题翻译：多波段带隙碲化镉光电器件及其制造方法
公开(公告)号：US08084682B2
公开(公告)日：2011-12-27
申请号：US12381166
申请日：2009-03-09
申请人： Yung-Tin Chen
发明人： Yung-Tin Chen
IPC分类号： H01L31/00
CPC分类号： H01L31/02963 , H01L31/0725 , H01L31/073 , H01L31/1836 , Y02E10/543 , Y02P70/521
摘要： A heterojunction photovoltaic device for the production of electrical energy in response to the incident light includes an optically transparent substrate, a front contact formed of an transparent conductive oxide for collecting light generated charge carriers, an n-type window layer formed of cadmium sulfide or zinc sulfide, a p-type absorber structure disposed on the window layer, thereby forming a rectification junction therebetween, and a back contact comprising at least one metal layer. The p-type absorber structure has a plurality of p-type absorber layers in contiguous contact. Each absorber layer contains cadmium as a principal constituent and has a different composition and a different band gap energy. The first absorber layer is in contiguous contact with the n-type window layer. The band gap energy progressively decreases from the first absorber layer to the last absorber layer in the p-type absorber structure.
摘要翻译：用于响应于入射光产生电能的异质结光伏器件包括光学透明衬底，由用于收集产生光的载流子的透明导电氧化物形成的前触点，由硫化镉或锌形成的n型窗口层硫化物，设置在窗口层上的p型吸收体结构，从而在它们之间形成整流接头，以及包括至少一个金属层的背面接触。 p型吸收体结构具有连续接触的多个p型吸收体层。每个吸收层包含镉作为主要成分并具有不同的组成和不同的带隙能量。第一吸收层与n型窗口层连续接触。带间隙能量从p型吸收体结构中的第一吸收层向最后一个吸收层逐渐减小。

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