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71. 发明授权

US06906366B2 Single transistor ferroelectric transistor structure with high-k insulator 失效
标题翻译：具有高k绝缘体的单晶体管铁电晶体管结构
公开(公告)号：US06906366B2
公开(公告)日：2005-06-14
申请号：US10441661
申请日：2003-05-20
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/3105 , H01L21/316 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/02189 , H01L21/02197 , H01L21/02271 , H01L21/0228 , H01L21/28291 , H01L21/31053 , H01L21/31604 , H01L21/31691 , H01L29/516 , H01L29/66545 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and a high-k insulator is provided. The high-k insulator may serve as both a gate dielectric and an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing a high-k insulator, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
摘要翻译：提供了具有铁电栅极和高k绝缘体的铁电晶体管栅极结构。高k绝缘体可以用作栅极电介质和绝缘体，以减少或消除氧或氢扩散到铁电栅极中。还提供了形成铁电栅极结构的方法。该方法包括以下步骤：形成牺牲栅极结构，去除牺牲栅极结构，沉积高k绝缘体，沉积铁电材料，使用CMP抛光铁电材料，以及形成覆盖铁电材料的顶部电极。

72. 发明授权

US06819583B2 Ferroelectric resistor non-volatile memory array 失效
标题翻译：铁电电阻非易失性存储器阵列
公开(公告)号：US06819583B2
公开(公告)日：2004-11-16
申请号：US10345726
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
摘要翻译：铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

73. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

74. 发明授权

US06759250B2 Deposition method for lead germanate ferroelectric structure with multi-layered electrode 失效
标题翻译：具有多层电极的锗酸铅铁电结构沉积方法
公开(公告)号：US06759250B2
公开(公告)日：2004-07-06
申请号：US10196503
申请日：2002-07-15
申请人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31604 , H01L21/31691 , H01L28/75
摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
摘要翻译：提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。还提供了形成上述多层电极铁电体结构体的方法。

75. 发明授权

US06720258B2 Method of fabricating a nickel silicide on a substrate 有权
标题翻译：在衬底上制造硅化镍的方法
公开(公告)号：US06720258B2
公开(公告)日：2004-04-13
申请号：US10319313
申请日：2002-12-12
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.
摘要翻译：集成电路器件及其制造方法包括在（100）Si上的外延硅化镍，或者由钴中间层制造的在非晶Si上的稳定的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积钴（Co）界面层。钴中间层通过由钴中间层与镍和硅的反应形成的钴/镍/硅合金层调节Ni原子的通量，使得Ni原子以相似的速率到达Si界面，即没有任何取向偏好，从而形成均匀的硅化镍层。可以将镍硅化物退火以形成均匀的结晶二硅化镍。因此，实现了（100）Si或非晶Si上的单晶硅化镍，其中硅化镍具有改进的稳定性并可用于超浅结结器件中。

76. 发明授权

US06682995B2 Iridium conductive electrode/barrier structure and method for same 失效
标题翻译：铱导电电极/屏障结构及方法相同
公开(公告)号：US06682995B2
公开(公告)日：2004-01-27
申请号：US10317742
申请日：2002-12-11
申请人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
发明人： Fengyan Zhang , Jer-shen Maa , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/456 , H01L21/28291 , H01L28/55 , H01L28/65
摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.
摘要翻译：已经提供了具有高温稳定性的导电阻挡层，其可用作铁电电容器电极。该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。已经发现，分离硅衬底与Ir膜与中间相邻的钽（Ta）膜非常有效地抑制层之间的扩散。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。这种Ir / TaN结构保护了硅界面，从而使粘附，电导，小丘和剥离问题最小化。使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。还提供了形成多层Ir导电结构和Ir铁电电极的方法。

77. 发明授权

US06531324B2 MFOS memory transistor & method of fabricating same 失效
公开(公告)号：US06531324B2
公开(公告)日：2003-03-11
申请号：US09820039
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/516 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

78. 发明授权

US06495378B2 Ferroelastic lead germanate thin film and deposition method 有权
标题翻译：铁硬脂酸铅薄膜和沉积方法
公开(公告)号：US06495378B2
公开(公告)日：2002-12-17
申请号：US09814273
申请日：2001-03-21
申请人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
发明人： Tingkai Li , Fengyan Zhang , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , C23C16/40 , H01L21/02271 , H01L21/31604 , H01L21/31691
摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.
摘要翻译：提供Pb3GeO5相PGO薄膜。该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。该方法将Pd和锗在溶剂中混合。将溶液加热以形成分解的前体蒸汽。该方法提供沉积温度和压力。沉积的膜也被退火以增强膜的铁弹性特征。还提供了由本发明PGO膜制成的铁弹性电容器。

79. 发明授权

US06468901B1 Nickel silicide including iridium for use in ultra-shallow junctions with high thermal stability and method of manufacturing the same 有权
标题翻译：包括用于具有高热稳定性的超浅结的铱的硅化镍及其制造方法
公开(公告)号：US06468901B1
公开(公告)日：2002-10-22
申请号：US09847873
申请日：2001-05-02
申请人： Jer-shen Maa , Yoshi Ono , Fengyan Zhang
发明人： Jer-shen Maa , Yoshi Ono , Fengyan Zhang
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： An integrated circuit device, and a method of manufacturing the same, including nickel silicide on a silicon substrate fabricated with an iridium interlayer. In one embodiment the method comprises depositing an iridium (Ir) interface layer between the Ni and Si layers prior to the silicidation reaction. The thermal stability is much improved by adding the thin iridium layer. This is shown by the low junction leakage current of the ultra-shallow junction, and by the low sheet resistance of the silicide, even after annealing at 850° C.
摘要翻译：一种集成电路器件及其制造方法，包括用铱中间层制造的硅衬底上的硅化镍。在一个实施方案中，该方法包括在硅化反应之前在Ni和Si层之间沉积铱（Ir）界面层。通过添加薄铱层，热稳定性大大提高。即使在850℃退火之后，超浅结的低结漏电流和硅化物的薄片电阻也被示出。

80. 发明授权

US06190963B1 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same 有权
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same$
标题翻译：复合铱金属 - 氧阻隔结构与难熔金属伴侣屏障及其方法相同
公开(公告)号：US06190963B1
公开(公告)日：2001-02-20
申请号：US09316661
申请日：1999-05-21
申请人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
发明人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.
摘要翻译：已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。结果，不形成铱硅化物产物，这降低了电极界面的特性。也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

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