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71. 发明申请

US20140046466A1 INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
标题翻译：使用性能路径测试结果的集成电路产品线优化
公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

72. 发明授权

US08539429B1 System yield optimization using the results of integrated circuit chip performance path testing 有权
标题翻译：系统产量优化采用集成电路芯片性能路径测试的结果
公开(公告)号：US08539429B1
公开(公告)日：2013-09-17
申请号：US13572954
申请日：2012-08-13
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725
摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
摘要翻译：公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关其中包含先前经过性能路径测试的那些IC芯片。基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统满足目标系统的性能价值）。可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。

73. 发明申请

US20130085726A1 INTEGRATED CIRCUIT DESIGN SIMULATION MATRIX INTERPOLATION 有权
标题翻译：集成电路设计仿真矩阵插值
公开(公告)号：US20130085726A1
公开(公告)日：2013-04-04
申请号：US13251517
申请日：2011-10-03
申请人： Peter A. Habitz , Amol A. Joshi
发明人： Peter A. Habitz , Amol A. Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.
摘要翻译：方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

74. 发明申请

US20120124542A1 Method and System for Optimizing a Device With Current Source Models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

75. 发明授权

US07856607B2 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
标题翻译：用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法
公开(公告)号：US07856607B2
公开(公告)日：2010-12-21
申请号：US11934146
申请日：2007-11-02
申请人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F11/24 , G01R31/31835
摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
摘要翻译：一种提高高速结构测试（ASST）实用性的系统。在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。第三种方法是选择逻辑电路的节点作为关键性分析的函数。第四种装置根据所选节点的临界概率来选择定时路径。第五装置为每个所选定时路径生成ASST模式。提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

76. 发明授权

US06624651B1 Kerf circuit for modeling of BEOL capacitances 有权
标题翻译：用于BEOL电容建模的Kerf电路
公开(公告)号：US06624651B1
公开(公告)日：2003-09-23
申请号：US09684849
申请日：2000-10-06
申请人： David M. Fried , Peter A. Habitz
发明人： David M. Fried , Peter A. Habitz
IPC分类号： G01R3126
CPC分类号： G01R31/006
摘要： A kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a “bay” that can be configured to test one particular capacitance. The clock circuit allows the capacitance testing circuits to charge and discharge the capacitive structures being tested. By having a number of different capacitance testing circuits, capacitances of many different structures may be tested at one time. This is particularly true if the kerf circuit is repeated several or many times, with each different kerf circuit containing different capacitive testing circuits that themselves contain different capacitive structures. The kerf circuit interfaces to testing equipment through pads. The pads connect to each capacitive testing circuit and allow capacitance measurements to be performed by measuring current.
摘要翻译：公开了一种用于线路后端（BEOL）电容建模的切口电路。切口电路包含连接到多个电容测试电路的时钟电路。每个电容测试电路都作为一个“间隔”，可以配置为测试一个特定的电容。时钟电路允许电容测试电路对被测试的电容结构进行充电和放电。通过具有多个不同的电容测试电路，可以一次测试许多不同结构的电容。如果切割电路重复数次或多次，则特别如此，每个不同的切屑回路包含不同的电容测试电路，它们本身包含不同的电容结构。切口电路通过焊盘与测试设备接口。焊盘连接到每个电容测试电路，并通过测量电流来进行电容测量。

77. 发明授权

US06519752B1 Method of performing parasitic extraction for a multi-fingered transistor 失效
标题翻译：对多指晶体管进行寄生提取的方法
公开(公告)号：US06519752B1
公开(公告)日：2003-02-11
申请号：US09561096
申请日：2000-04-28
申请人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
发明人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
摘要翻译：一种用于对多指装置执行寄生提取的方法和结构，包括：建立装置的手指的最大处理宽度，将超过最大宽度的装置的手指分成子手指，确定手指中是否有手指子手指具有类似的特征，将具有类似特征的手指和子手指组合成组合手指，并从手指，子手指和组合手指中提取寄生值。

78. 发明授权

US06460167B1 Efficient system for multi-level shape interactions 失效
标题翻译：用于多层次形状相互作用的高效系统
公开(公告)号：US06460167B1
公开(公告)日：2002-10-01
申请号：US09559800
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz
发明人： L. William Dewey, III , Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.
摘要翻译：用于评估集成电路设计的结构和方法包括在集成电路结构的先前层上添加集成电路设计的替代层，识别替代层和先前层中的区域和边缘的数据库指针，去除数据库指针上一层的区域与替代层重叠，将取代层和先前层分类为上一层，并重复该方法直到评估集成电路的所有层。

79. 发明授权

US5761080A Method and apparatus for modeling capacitance in an integrated circuit 失效
标题翻译：用于对集成电路中的电容进行建模的方法和装置
公开(公告)号：US5761080A
公开(公告)日：1998-06-02
申请号：US561647
申请日：1995-11-22
申请人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
发明人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y10S706/921
摘要： According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.
摘要翻译：根据本实施例，公开了一种用于计算半导体器件中的寄生电容的方法。根据优选方法，提供了包含半导体器件的形状的布局文件。然后将布局文件的尺寸调整为晶圆尺寸，以反映实际的生产设备。然后，布局文件的形状被分割成更简单的形状，通常是称为块的邻接矩形。然后，每个瓦片被分解成重叠和边缘电容分量，每个部件相对于其电容元件具有均匀的电容环境。因此，可以有效利用资源来准确地计算半导体器件的寄生电容。此外，优选实施例容易适应于广泛的技术类型。

80. 发明授权

US08239810B2 Method and system for optimizing a device with current source models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US08239810B2
公开(公告)日：2012-08-07
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

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