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71. 发明申请

US20060040413A1 Pt/PGO etching process for FeRAM applications 失效
公开(公告)号：US20060040413A1
公开(公告)日：2006-02-23
申请号：US10923381
申请日：2004-08-20
申请人： Fengyan Zhang , Bruce Ulrich , Lisa Stecker , Sheng Hsu
发明人： Fengyan Zhang , Bruce Ulrich , Lisa Stecker , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L21/32139 , H01L21/32136 , H01L27/1085 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

72. 发明申请

US20050266686A1 Method of substrate surface treatment for RRAM thin film deposition 有权
标题翻译： RRAM薄膜沉积的基板表面处理方法
公开(公告)号：US20050266686A1
公开(公告)日：2005-12-01
申请号：US10855088
申请日：2004-05-27
申请人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
发明人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
IPC分类号： C23C18/12 , C30B23/02 , C30B29/24 , H01L21/44 , H01L45/00
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1241 , C23C18/1283 , C30B23/02 , C30B29/24 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.
摘要翻译：制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

73. 发明申请

US20050243630A1 Memory cell with an asymmetrical area 有权
标题翻译：具有不对称区域的存储单元
公开(公告)号：US20050243630A1
公开(公告)日：2005-11-03
申请号：US11174034
申请日：2005-07-01
申请人： Sheng Hsu , Fengyan Zhang
发明人： Sheng Hsu , Fengyan Zhang
IPC分类号： H01L21/28 , G11C11/15 , G11C13/00 , H01L21/3205 , H01L21/8239 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/115 , H01L27/22 , H01L27/24 , H01L29/68 , H01L43/08 , H01L45/00 , G11C7/00
CPC分类号： H01L27/105 , G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/1052 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.
摘要翻译：提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

74. 发明申请

US20050151210A1 In2O3 thin film resistivity control by doping metal oxide insulator for MFMox device applications 有权
标题翻译： In2O3薄膜电阻率控制通过掺杂金属氧化物绝缘子用于MFMox器件应用
公开(公告)号：US20050151210A1
公开(公告)日：2005-07-14
申请号：US10755419
申请日：2004-01-12
申请人： Tingkai Li , Sheng Hsu
发明人： Tingkai Li , Sheng Hsu
IPC分类号： H01L21/28 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28291 , H01L29/78391
摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.
摘要翻译：本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了捕获的电荷效应并导致存储保持率的提高特点电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

75. 发明申请

US20050124112A1 Asymmetric-area memory cell 有权
标题翻译：非对称区记忆单元
公开(公告)号：US20050124112A1
公开(公告)日：2005-06-09
申请号：US10730726
申请日：2003-12-08
申请人： Sheng Hsu , Fengyan Zhang
发明人： Sheng Hsu , Fengyan Zhang
IPC分类号： H01L21/28 , G11C11/15 , G11C13/00 , H01L21/3205 , H01L21/8239 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/115 , H01L27/22 , H01L27/24 , H01L29/68 , H01L43/08 , H01L45/00 , H01L21/8242
CPC分类号： H01L27/105 , G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/1052 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.
摘要翻译：提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

76. 发明申请

US20050083757A1 Cross-point resistor memory array 有权
标题翻译：交叉点电阻存储器阵列
公开(公告)号：US20050083757A1
公开(公告)日：2005-04-21
申请号：US10971204
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , G11C7/00
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/72 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。电阻交叉点存储器件通过在衬底内掺杂一行极性形成，然后将相反极性的线的掺杂区域形成二极管。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

77. 发明申请

US20050079727A1 One mask PT/PCMO/PT stack etching process for RRAM applications 有权
标题翻译：用于RRAM应用的一个掩模PT / PCMO / PT堆叠蚀刻工艺
公开(公告)号：US20050079727A1
公开(公告)日：2005-04-14
申请号：US10677008
申请日：2003-09-30
申请人： Fengyan Zhang , Sheng Hsu
发明人： Fengyan Zhang , Sheng Hsu
IPC分类号： H01L21/28 , G11C13/00 , H01L21/02 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L45/00 , H01L21/302 , H01L21/461
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31122 , H01L21/32136 , H01L27/101 , H01L28/55 , H01L28/65 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.
摘要翻译：一种干法蚀刻PCMO堆叠的方法，包括制备衬底; 沉积阻挡层; 沉积底部电极; 沉积PCMO薄膜; 沉积顶部电极; 沉积硬掩模层; 应用光刻胶和图案化; 蚀刻硬掩模层; 干法蚀刻顶部电极; 在多步蚀刻工艺中干法刻蚀PCMO层; 干蚀下层电极; 并完成基于PCMO的设备。

78. 发明申请

US20090309504A1 COLOR-CONTROLLABLE LIGHT STRING 审中-公开
标题翻译：彩色控制灯
公开(公告)号：US20090309504A1
公开(公告)日：2009-12-17
申请号：US12139287
申请日：2008-06-13
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： H05B37/02
CPC分类号： H05B33/0842 , H05B33/0803 , H05B33/0857 , H05B33/0863
摘要： A color-controllable light string has a control box and a light string composed of lighting units. The control box provides a DC power to the lighting units through two power wires and transmits a synchronization signal to the lighting units through a signal wire. Each of the lighting units has a waterproof assembly constructing a sealed environment and an LED circuit board with multiple LEDs of different colors mounted in the sealed environment to provide colorful lights by mixing and activating proper LEDs.
摘要翻译：颜色可控的灯串具有控制箱和由照明单元组成的灯串。控制箱通过两根电源线为照明装置提供直流电源，并通过信号线将同步信号发送到照明装置。每个照明单元具有构造密封环境的防水组件和安装在密封环境中的具有不同颜色的多个LED的LED电路板，以通过混合和激活适当的LED来提供彩色光。

79. 发明申请

US20070109835A1 Cross-point RRAM memory array having low bit line crosstalk 有权
公开(公告)号：US20070109835A1
公开(公告)日：2007-05-17
申请号：US11283135
申请日：2005-11-17
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0023 , G11C13/004 , G11C2213/77
摘要： A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said word lines, and wherein a cross-point is formed between said word lines and said bit lines. A memory resistor located between said word lines and said bit lines at each cross-point. A high-open-circuit-voltage gain, bit line sensing differential amplifier circuit located on each bit line, including a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state.

80. 发明申请

US20070045694A1 Method of selecting a RRAM memory material and electrode material 审中-公开
标题翻译：选择RRAM记忆材料和电极材料的方法
公开(公告)号：US20070045694A1
公开(公告)日：2007-03-01
申请号：US11215484
申请日：2005-08-30
申请人： Sheng Hsu
发明人： Sheng Hsu
IPC分类号： H01L29/76
CPC分类号： H01L45/1253 , G11C13/00 , G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of determining a memory material and an associated electrode material for use in a RRAM device includes selecting a memory material having an inner orbital having less than a full quota of electrons and a narrow, outer conductive orbital; and selecting an associated electrode material for injecting a packet of electrons into the selected memory material when subjected to a narrow-width electric pulse, and which recovers the packet of electrons when subjected to a large-width electric pulse.
摘要翻译：一种确定用于RRAM设备的存储材料和相关电极材料的方法包括选择具有小于全部电子配额的内轨道和窄的外导电轨道的存储材料; 以及当经受窄宽电脉冲时选择用于将电子包注入所选择的存储材料中的相关联的电极材料，并且当经受大宽度电脉冲时，电子包回收。

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