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71. 发明授权

US07138701B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07138701B2
公开(公告)日：2006-11-21
申请号：US10605483
申请日：2003-10-02
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/00 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

72. 发明授权

US07119401B2 Tunable semiconductor diodes 有权
标题翻译：可调谐半导体二极管
公开(公告)号：US07119401B2
公开(公告)日：2006-10-10
申请号：US10707722
申请日：2004-01-07
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： H01L29/66136 , H01L27/0255 , H01L29/8611 , H01L29/8618 , H01L2924/0002 , H01L2924/00
摘要： A diode structure that facilitates tuning the breakdown voltage of the diode structure, and a method for forming and operating the diode structure. In a P− substrate, a N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is implanted in the substrate. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.
摘要翻译：有助于调谐二极管结构的击穿电压的二极管结构，以及用于形成和操作二极管结构的方法。在P-衬底中，植入N +层。 N +层的开口尺寸影响二极管结构的击穿电压。在N +层上，在衬底中注入N层。然后，形成P +区域作为二极管结构的阳极。可以在衬底的表面上形成N +区以用作二极管结构的阴极。通过在制造期间改变N +层中的开口的尺寸，可以将二极管结构的击穿电压改变（调谐）至期望的值。

73. 发明授权

US06996786B2 Latch-up analysis and parameter modification 失效
标题翻译：锁定分析和参数修改
公开(公告)号：US06996786B2
公开(公告)日：2006-02-07
申请号：US10605443
申请日：2003-09-30
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A latch-up analysis and parameter modification system, method and program product that analyzes a circuit design for latch-up sensitivity and allows for modifications of the circuit design to avoid latch-up of the circuit while improving the density and overall performance of the circuit are disclosed. Latch-up of a circuit design is analyzed through identifying an injector source and a collector circuit, at least one of the injector source and the collector circuit having a parameter, providing latch-up criteria for the collector circuit, and determining latch-up sensitivity of the collector circuit based on the latch-up criteria and the parameter. Then, the parameter may be modified to adjust latch-up sensitivity, and latch-up sensitivity of the collector circuit is determined based on the latch-up criteria and the modified parameter.
摘要翻译：一种闭锁分析和参数修改系统，方法和程序产品，分析电路设计的闩锁灵敏度，并允许修改电路设计，以避免电路闭锁，同时提高电路的密度和整体性能被披露。电路设计的锁定通过识别一个注射源和一个集电极电路进行分析，至少有一个注入源和集电极电路具有一个参数，为集电极电路提供闭锁准则，并确定闩锁灵敏度基于闭锁准则和参数的集电极电路。然后，可以修改参数以调整闩锁灵敏度，并且基于闩锁准则和修改的参数来确定集电极电路的锁存灵敏度。

74. 发明授权

US06943578B1 Method and application of PICA (picosecond imaging circuit analysis) for high current pulsed phenomena 失效
标题翻译：用于大电流脉冲现象的PICA（皮秒成像电路分析）的方法和应用
公开(公告)号：US06943578B1
公开(公告)日：2005-09-13
申请号：US10814962
申请日：2004-03-31
申请人： Naoko Pia Sanda , Steven H. Voldman , Alan J. Weger
发明人： Naoko Pia Sanda , Steven H. Voldman , Alan J. Weger
IPC分类号： G01R31/00 , G01R31/28 , G01R31/308 , G01R31/311 , G06F17/50 , H01L21/66 , G01R31/26
CPC分类号： G01R31/308
摘要： A method, system and apparatus are provided for operating a Picosecond Imaging Circuit Analysis (PICA)/high current source system include applying pulses from a high current pulse source to a Device Under Test (DUT). A photosensor detects photon emissions from the DUT. Signals from the photosensor are used to map photon emissions from the DUT. Data processing means relate the photon emissions to specific features of the DUT.
摘要翻译：提供了一种用于操作Picosecond成像电路分析（PICA）/高电流源系统的方法，系统和装置，包括将来自高电流脉冲源的脉冲施加到被测设备（DUT）。光电传感器检测来自DUT的光子发射。来自光电传感器的信号用于映射DUT的光子发射。数据处理手段将光子发射与DUT的特定特征相关联。

75. 发明授权

US06895372B1 System and method for VLSI visualization 失效
标题翻译： VLSI可视化的系统和方法
公开(公告)号：US06895372B1
公开(公告)日：2005-05-17
申请号：US09406663
申请日：1999-09-27
申请人： Daniel R. Knebel , Mark A. Lavin , Jamie Moreno , Stanislav Polonsky , Pia N. Sanda , Steven H. Voldman
发明人： Daniel R. Knebel , Mark A. Lavin , Jamie Moreno , Stanislav Polonsky , Pia N. Sanda , Steven H. Voldman
IPC分类号： G06F17/50 , H01L21/76
CPC分类号： G06F17/5022
摘要： A method and system for visualizing circuit operation. In the method device activity is obtained based on one or more of measured or simulated activity. The device activity is expressed in a representation, and the expressed activity is represented in a visual form. One suitable form of activity is the simulated version of the PICA slow motion movie. The invention may apply to other simulated design data vies as well, such as switch level simulation, current density simulation, and power density simulation.
摘要翻译：一种用于可视化电路操作的方法和系统。在该方法中，基于测量或模拟活动中的一个或多个获得装置活动。设备活动以表示形式表达，表达的活动以视觉形式表示。一种合适的活动形式是PICA慢动作电影的模拟版本。本发明也可以应用于其他模拟设计数据，例如开关级仿真，电流密度模拟和功率密度模拟。

76. 发明授权

US06680520B2 Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses 有权
标题翻译：使用保险丝和反熔丝形成精密MIM易熔电路元件的方法和结构
公开(公告)号：US06680520B2
公开(公告)日：2004-01-20
申请号：US09525088
申请日：2000-03-14
申请人： Steven H. Voldman , Anthony K. Stamper
发明人： Steven H. Voldman , Anthony K. Stamper
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L23/5223 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provide a nominal circuit element value close in value to the desired value. Additional trim circuit elements are joined to the nominal circuit element through links. The links are fusible links or antifuses. By selectively blowing the fusible links or fusing the antifuses, trim circuit elements are added or subtracted to personalize the value of the nominal circuit element. A capacitor is used in an illustrative example.
摘要翻译：本发明描述了一种用于制造精密电路元件的装置和方法。特别地，电路元件被制造为集成电路组件的一部分。电路元件的处理使得提供与期望值接近的额定电路元件值。附加的微调电路元件通过链路连接到标称电路元件。链接是可熔链接或反熔丝。通过选择性地吹入可熔连接件或熔合反熔丝，对微调电路元件进行加法或减法以个性化标称电路元件的值。在说明性示例中使用电容器。

77. 发明授权

US06548338B2 Integrated high-performance decoupling capacitor and heat sink 失效
标题翻译：集成高性能去耦电容和散热片
公开(公告)号：US06548338B2
公开(公告)日：2003-04-15
申请号：US09764504
申请日：2001-01-17
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译：一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。

78. 发明授权

US06429482B1 Halo-free non-rectifying contact on chip with halo source/drain diffusion 有权
标题翻译：光环/漏极扩散芯片上的无光非整流接触
公开(公告)号：US06429482B1
公开(公告)日：2002-08-06
申请号：US09589719
申请日：2000-06-08
申请人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
发明人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
IPC分类号： H01L2976
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.
摘要翻译：半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。卤素扩散与整流接触扩散相邻，并且没有卤素扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

79. 发明授权

US06426244B2 Process of forming a thick oxide field effect transistor 失效
标题翻译：形成厚氧化物场效应晶体管的工艺
公开(公告)号：US06426244B2
公开(公告)日：2002-07-30
申请号：US09903820
申请日：2001-07-12
申请人： Michael J. Hargrove , Mario M. Pelella , Steven H. Voldman
发明人： Michael J. Hargrove , Mario M. Pelella , Steven H. Voldman
IPC分类号： H01L2100
CPC分类号： H01L27/1203 , H01L27/0266 , H01L29/4908 , H01L29/78615 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate s formed during the BEOL process. The transistor may by a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.
摘要翻译：提供ESD保护的SOI场效应晶体管结构。该结构具有源，漏，体和门。栅极由厚的氧化物层和金属接触形成。在BEOL过程中形成门。晶体管可以由p型晶体管或n型晶体管构成。晶体管可以将其漏极连接到栅极，主体或栅极和主体两者。当用作保护装置时，漏极连接到信号焊盘，源极连接到潜在的参考电压。

80. 发明授权

US06380570B1 Gate overvoltage control networks 有权
标题翻译：门过压控制网络
公开(公告)号：US06380570B1
公开(公告)日：2002-04-30
申请号：US09556211
申请日：2000-04-21
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L2972
CPC分类号： H01L27/0251
摘要： A semiconductor device which comprises an anode of a first conductivity type; a cathode of a second conductivity type; a device region separating said anode and said cathode, said device region comprises at least a gate dielectric; and an overvoltage control network coupled to the gate dielectric of said device region, wherein said overvoltage control network substantially reduces electrical overstress of said gated device.
摘要翻译：一种半导体器件，包括第一导电类型的阳极; 第二导电类型的阴极; 分离所述阳极和所述阴极的器件区域，所述器件区域至少包括栅极电介质; 以及耦合到所述器件区域的栅极电介质的过电压控制网络，其中所述过电压控制网络基本上减小所述门控器件的电应力。

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