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71. 发明申请

US20070004162A1 Capacitor structure for a logic process 有权
标题翻译：逻辑过程的电容结构
公开(公告)号：US20070004162A1
公开(公告)日：2007-01-04
申请号：US11170504
申请日：2005-06-29
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： H01L21/331
CPC分类号： H01L27/108 , H01L27/1085 , H01L28/40
摘要： A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
摘要翻译：公开了制造金属绝缘体金属（MIM）电容器的制造工艺改进。 MIM电容器可以用在诸如DRAM的存储器单元中，并且还可以被集成到诸如微处理器的逻辑处理中。用于生成MIM电容器的处理适用于当前的逻辑处理技术。描述和要求保护其他实施例。

72. 发明申请

US20060140041A1 Leakage current management 有权
标题翻译：漏电管理
公开(公告)号：US20060140041A1
公开(公告)日：2006-06-29
申请号：US11027696
申请日：2004-12-28
申请人： Arman Vassighi , Ali Keshavarzi , Vivek De
发明人： Arman Vassighi , Ali Keshavarzi , Vivek De
IPC分类号： G11C8/00
CPC分类号： G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： A thermal feedback loop controls leakage current during burn-in of a circuit.
摘要翻译：热反馈回路控制电路老化期间的漏电流。

73. 发明申请

US20060067152A1 Crosspoint memory array utilizing one time programmable antifuse cells 有权
公开(公告)号：US20060067152A1
公开(公告)日：2006-03-30
申请号：US10954537
申请日：2004-09-29
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C17/18 , G11C5/06
CPC分类号： G11C17/16
摘要： Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

74. 发明申请

US20060067133A1 Apparatus and method for a one-phase write to a one-transistor memory cell array 失效
标题翻译：用于单相写入单晶体管存储单元阵列的装置和方法
公开(公告)号：US20060067133A1
公开(公告)日：2006-03-30
申请号：US10956407
申请日：2004-09-30
申请人： Yibin Ye , Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Gerhard Schrom , Vivek De
发明人： Yibin Ye , Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Gerhard Schrom , Vivek De
IPC分类号： G11C7/10
CPC分类号： G11C11/404 , G11C2211/4016
摘要： A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
摘要翻译：用于单相写入单晶体管存储单元阵列的方法和装置。在一个实施例中，该方法包括对存储器单元阵列的选定字线的单相写入。一旦选择了字线，逻辑零值被存储在存储单元阵列的选定字线的至少一个存储单元中。同时，逻辑0值存储在所选择的存储单元阵列的选定字线的至少一个存储单元中。描述和要求保护其他实施例。

75. 发明申请

US20060014331A1 Floating-body DRAM in tri-gate technology 有权
标题翻译：三门技术中的浮体DRAM
公开(公告)号：US20060014331A1
公开(公告)日：2006-01-19
申请号：US10879480
申请日：2004-06-30
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
摘要翻译：浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

76. 发明授权

US06903984B1 Floating-body DRAM using write word line for increased retention time 失效
标题翻译：使用写字线的浮体DRAM增加保留时间
公开(公告)号：US06903984B1
公开(公告)日：2005-06-07
申请号：US10748222
申请日：2003-12-31
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
IPC分类号： G11C11/404 , G11C11/408 , H01L27/108 , H01L29/78 , G11C7/00
CPC分类号： H01L27/108 , G11C11/404 , G11C11/4085 , H01L29/7841
摘要： A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
摘要翻译： DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。

77. 发明授权

US06828638B2 Decoupling capacitors for thin gate oxides 有权
标题翻译：薄栅氧化物去耦电容器
公开(公告)号：US06828638B2
公开(公告)日：2004-12-07
申请号：US09469406
申请日：1999-12-22
申请人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
发明人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
IPC分类号： H01L2976
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

78. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

79. 发明授权

US06411156B1 Employing transistor body bias in controlling chip parameters 有权
标题翻译：采用晶体管体偏置来控制芯片参数
公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译：在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号控制电路。在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

80. 发明授权

US06300819B1 Circuit including forward body bias from supply voltage and ground nodes 失效
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

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