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71. 发明授权

US07585768B2 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US07585768B2
公开(公告)日：2009-09-08
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

72. 发明申请

US20090108257A1 CRITICAL DIMENSION FOR TRENCH AND VIAS 有权
标题翻译： TRENCH和VIAS的关键尺寸
公开(公告)号：US20090108257A1
公开(公告)日：2009-04-30
申请号：US11927658
申请日：2007-10-29
申请人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
发明人： Hai Cong , Yan San Li , Chun Hui Low , Yelehanka Ramachandramurthy Pradeep , Liang Choo Hsia
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.
摘要翻译：包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。沟槽形成在IC的外围，用作保护环。

73. 发明申请

US20090088002A1 METHOD OF FABRICATING A NITROGENATED SILICON OXIDE LAYER AND MOS DEVICE HAVING SAME 有权
标题翻译：制备氮化硅氧化物层的方法和具有其的MOS器件
公开(公告)号：US20090088002A1
公开(公告)日：2009-04-02
申请号：US11862865
申请日：2007-09-27
申请人： Jinping Liu , Ben Ong , Zhengquan Zhang , Jae Gon Lee , Lydia Wong , Bin Yang , K. H. See , Meisheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Ben Ong , Zhengquan Zhang , Jae Gon Lee , Lydia Wong , Bin Yang , K. H. See , Meisheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/31
CPC分类号： H01L21/3143 , H01L21/0214 , H01L21/02332 , H01L21/28202 , H01L21/31155 , H01L29/513 , H01L29/518
摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.
摘要翻译：一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。通过施加氮等离子体将氮引入到氧化硅层中。在施加氮等离子体之后，将氧化硅层退火。重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

74. 发明授权

US07445978B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS 有权
标题翻译：腐蚀后去除间隔物的方法，以增强接触蚀刻停止衬垫在MOS上的应力
公开(公告)号：US07445978B2
公开(公告)日：2008-11-04
申请号：US11122666
申请日：2005-05-04
申请人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
发明人： Young Way Teh , Yong Meng Lee , Chung Woh Lai , Wenhe Lin , Khee Yong Lim , Wee Leng Tan , John Sudijono , Hui Peng Koh , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864
摘要： An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要翻译：从NMOS晶体管的栅极去除间隔物的示例性过程。在NMOS和PMOS晶体管和衬底上形成应力产生层。在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。应力产生层优选为拉伸氮化物层。应力产生层优选为接触蚀刻停止衬层。在一个实施例中，栅极，源极和漏极区域在形成应力产生层之前具有硅化物层。该实施例改善了NMOS晶体管的性能。

75. 发明授权

US07338886B2 Implantation-less approach to fabricating strained semiconductor on isolation wafers 有权
标题翻译：无离子方法在隔离晶圆上制造应变半导体
公开(公告)号：US07338886B2
公开(公告)日：2008-03-04
申请号：US11107712
申请日：2005-04-15
申请人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jinping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02395 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76262 , H01L29/78 , Y10S438/933
摘要： A method of fabricating a semiconductor substrate includes forming a buffer layer on the substrate. A Ge containing layer, such as a SiGe is formed over the buffer layer. The buffer layer includes defects at the interface of the substrate and buffer layer. The substrate is oxidized to transform the buffer layer to a buried oxide layer.
摘要翻译：制造半导体衬底的方法包括在衬底上形成缓冲层。在缓冲层之上形成Ge含Ge层，例如SiGe。缓冲层包括在衬底和缓冲层的界面处的缺陷。将衬底氧化以将缓冲层转变成掩埋氧化物层。

76. 发明授权

US07202140B1 Method to fabricate Ge and Si devices together for performance enhancement 有权
标题翻译：将Ge和Si器件制造在一起以提高性能的方法
公开(公告)号：US07202140B1
公开(公告)日：2007-04-10
申请号：US11297540
申请日：2005-12-07
申请人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
发明人： Chew Hoe Ang , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/30
CPC分类号： H01L27/0688 , H01L21/76256 , H01L21/8221 , H01L21/823807 , H01L2924/00011 , H01L2224/80001
摘要： A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs. We form second active devices on the second substrate.
摘要翻译：一种用于形成具有形成在两侧的器件的半导体结构的方法。提供第一基板和第二基板。第一衬底优选由Ge组成。第二衬底优选由硅组成。我们在第一衬底上形成第一电介质层。我们在第二衬底上形成第一绝缘层。我们键合第一介电层和第一介电层以形成第一结构。第一结构包括第一基底，绝缘层（组合的第一介电层和第一绝缘层）和第二基底。我们减少第一个基板的厚度。我们通过插塞穿过第一基底和绝缘层形成，并且至少部分地穿过第二基底。我们在第一衬底的表面上形成第一有源器件。我们在第一有源器件和第一衬底上形成第一覆盖层。我们减小第二基板的厚度以露出通孔塞。我们在第二个基板上形成第二个有源器件。

77. 发明授权

US07012022B2 Self-patterning of photo-active dielectric materials for interconnect isolation 失效
公开(公告)号：US07012022B2
公开(公告)日：2006-03-14
申请号：US10697745
申请日：2003-10-30
申请人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
发明人： Wuping Liu , Bei Chao Zhang , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/4846 , H01L21/76802 , H01L21/76807 , H01L21/76828 , H01L23/5329 , H01L2221/1026 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is created, this without the use of an overlying exposure mask of photoresist.

78. 发明授权

US06995078B2 Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch 有权
标题翻译：在具有大晶格失配的衬底上形成松散半导体缓冲层的方法
公开(公告)号：US06995078B2
公开(公告)日：2006-02-07
申请号：US10763305
申请日：2004-01-23
申请人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
发明人： Jin Ping Liu , Dong Kyun Sohn , Liang Choo Hsia
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/0262 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.
摘要翻译：已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长的分级第一硅锗层进行。该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

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