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71. 发明申请

US20060286794A1 Stacked structure for forming damascene structure, method of fabricating the stacked structure, and damascene process 有权
标题翻译：用于形成镶嵌结构的堆叠结构，制造堆叠结构的方法和镶嵌工艺
公开(公告)号：US20060286794A1
公开(公告)日：2006-12-21
申请号：US11322140
申请日：2005-12-28
申请人： Chin-Hsiang Lin , Chih-Chien Liu
发明人： Chin-Hsiang Lin , Chih-Chien Liu
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76826 , H01L21/76811 , H01L27/11524 , H01L27/11548 , H01L27/11556
摘要： A method of fabricating a stacked structure for forming a damascene process is described. A doped dielectric layer is formed on a substrate. A surface treatment is performed to the dielectric layer to make the dopant concentration in an upper surface layer of the dielectric layer lower than that in the other portions of the dielectric layer. A metal hard mask is then formed on the dielectric layer. Since the dopant conc. in the upper surface layer of the dielectric layer is lowered, the reaction between the metal hard mask and the dopant in the dielectric layer can be inhibited.
摘要翻译：描述了一种制造用于形成镶嵌工艺的层叠结构的方法。在衬底上形成掺杂介电层。对电介质层进行表面处理，使得电介质层的上表面层中的掺杂剂浓度低于电介质层的其它部分中的掺杂剂浓度。然后在电介质层上形成金属硬掩模。由于掺杂剂浓度在电介质层的上表层降低时，可以抑制金属硬掩模与电介质层中的掺杂剂之间的反应。

72. 发明申请

US20060165913A1 Method of reducing number of particals on low-k material layer 审中-公开
标题翻译：减少低k材料层上的物质数量的方法
公开(公告)号：US20060165913A1
公开(公告)日：2006-07-27
申请号：US11046049
申请日：2005-01-27
申请人： Bella Chen , Chin-Hsiang Lin , Chih-Chien Liu , Jerander Lai
发明人： Bella Chen , Chin-Hsiang Lin , Chih-Chien Liu , Jerander Lai
IPC分类号： H05H1/24
CPC分类号： C23C16/4405 , C23C16/401 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02334 , H01L21/02337 , H01L21/31633 , H01L21/76826
摘要： A method of reducing the number of particles on a low-k material layer is described. The low-k material layer is formed by a plasma enhanced chemical vapor deposition process, wherein a reaction gas, a cleaning gas, a high-frequency power and a low-frequency power are used. The method comprises turning off the reaction gas and the low-frequency power after the low-k material layer is formed, and continuing to provide the cleaning gas during a delay time.
摘要翻译：描述了一种减少低k材料层上的颗粒数量的方法。低k材料层通过等离子体增强化学气相沉积法形成，其中使用反应气体，清洁气体，高频功率和低频功率。该方法包括在形成低k材料层之后关闭反应气体和低频功率，并且在延迟时间内继续提供清洁气体。

73. 发明授权

US07078346B2 High density plasma chemical vapor deposition process 有权
公开(公告)号：US07078346B2
公开(公告)日：2006-07-18
申请号：US10902315
申请日：2004-07-29
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

74. 发明授权

US06905938B2 Method of forming interconnect structure with low dielectric constant 有权
标题翻译：形成具有低介电常数的互连结构的方法
公开(公告)号：US06905938B2
公开(公告)日：2005-06-14
申请号：US10315128
申请日：2002-12-10
申请人： Ming-Sheng Yang , Chih-Chien Liu
发明人： Ming-Sheng Yang , Chih-Chien Liu
IPC分类号： H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/76
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/318 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.
摘要翻译：本发明提供一种形成低介电常数金属间介电层的方法。该方法包括提供半导体衬底并在半导体衬底上形成第一电介质层。在第一电介质层中形成导体结构。通过使用导体结构作为蚀刻掩模来去除部分第一介电层。在导体结构之间形成第二电介质层，导体结构的介电常数小于第一介电层。第二电介质层也可选择地含有空气，以减少介电常数。

75. 发明授权

US06410106B1 Method of forming an intermetal dielectric layer 有权
公开(公告)号：US06410106B1
公开(公告)日：2002-06-25
申请号：US09759570
申请日：2001-01-11
申请人： Cheng-Yuan Tsai , Chih-Chien Liu , Ming-Sheng Yang
发明人： Cheng-Yuan Tsai , Chih-Chien Liu , Ming-Sheng Yang
IPC分类号： H05H124
摘要： A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

76. 发明授权

US06319814B1 Method of fabricating dual damascene 有权
标题翻译：双镶嵌方法
公开(公告)号：US06319814B1
公开(公告)日：2001-11-20
申请号：US09417830
申请日：1999-10-12
申请人： Cheng-Yuan Tsai , Chih-Chien Liu , Juan-Yuan Wu
发明人： Cheng-Yuan Tsai , Chih-Chien Liu , Juan-Yuan Wu
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/02131 , H01L21/02274 , H01L21/02304 , H01L21/31629 , H01L21/7681 , H01L21/76832
摘要： A method for fabricating dual damascene is to form an undoped silicate glass (USG) liner before forming a fluorinated silicate glass (FSG) layer which serves as an inter-metal dielectric (IMD) layer on a semiconductor substrate. As a result, the surface sensitivity is eliminated, while a FSG layer with a more uniform thickness and a higher reliability is obtained. In addition, the USG liner increases the adhesion between the FSG layer and other material layers, while no particles are easily formed thereon.
摘要翻译：制造双镶嵌的方法是在形成在半导体衬底上作为金属间电介质（IMD）层的氟化硅酸盐玻璃（FSG）层之前形成未掺杂的硅酸盐玻璃（USG）衬垫。结果，消除了表面灵敏度，而获得了具有更均匀厚度和更高可靠性的FSG层。此外，USG衬垫增加了FSG层和其它材料层之间的粘附性，而在其上不容易形成颗粒。

77. 发明授权

US06261977B1 Method for preventing an electrostatic chuck from being corroded during a cleaning process 失效
标题翻译：防止静电卡盘在清洗过程中被腐蚀的方法
公开(公告)号：US06261977B1
公开(公告)日：2001-07-17
申请号：US09391357
申请日：1999-09-08
申请人： Cheng-Yuan Tsai , Chih-Chien Liu , Juan-Yuan Wu
发明人： Cheng-Yuan Tsai , Chih-Chien Liu , Juan-Yuan Wu
IPC分类号： H01L21324
CPC分类号： H01L21/67069 , H01L21/6831 , H01L21/6833 , Y10S438/905 , Y10S438/906 , Y10S438/907
摘要： The present invention relates to a method for preventing an electrostatic chuck positioned at the bottom of a plasma vacuum chamber from being corroded during a cleaning process. The electrostatic chuck comprises a conductive substrate functioned as a lower electrode in a plasma process, and an insulating layer on the conductive substrate to electrically isolate the semiconductor wafer and the conductive substrate. The cleaning process involves a plasma process in which a fluorine-contained gas is injected into the plasma vacuum chamber to remove the chemical layer on the inner wall of the plasma vacuum chamber. A ceramic shutter made of SiC material is reposed on the electrostatic chuck and a high DC voltage is applied to the conductive substrate and the ceramic shutter which causes the ceramic shutter and the electrostatic chuck tightly stick together due to an electrostatic reaction. By doing so, the fluorine-contained gas cannot corrode the insulating layer under the ceramic shutter through the gap between the ceramic shutter and the electrostatic chuck.
摘要翻译：本发明涉及一种防止位于等离子体真空室底部的静电卡盘在清洗过程中被腐蚀的方法。静电卡盘包括在等离子体工艺中用作下电极的导电基板和导电基板上的绝缘层，以电绝缘半导体晶片和导电基板。清洗过程涉及等离子体处理，其中将含氟气体注入到等离子体真空室中以除去等离子体真空室的内壁上的化学层。由SiC材料制成的陶瓷快门被放置在静电卡盘上，并且高导电性基板和陶瓷快门上施加高的直流电压，导致陶瓷快门和静电卡盘由于静电反应紧紧地粘在一起。通过这样做，含氟气体不能通过陶瓷快门和静电卡盘之间的间隙腐蚀陶瓷快门下面的绝缘层。

78. 发明授权

US06248644B1 Method of fabricating shallow trench isolation structure 有权
标题翻译：制造浅沟槽隔离结构的方法
公开(公告)号：US06248644B1
公开(公告)日：2001-06-19
申请号：US09301210
申请日：1999-04-28
申请人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
发明人： Gwo-Shii Yang , Hsueh-Hao Shih , Chih-Chien Liu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.
摘要翻译：描述了制造浅沟槽隔离结构的方法。在基板上形成保护层。在衬底和保护层中形成沟槽。在衬底上形成氧化物层以填充沟槽。在潮湿的环境中进行湿致密化步骤。进行平坦化步骤直到保护层被暴露。形成浅沟槽隔离结构。

79. 发明授权

US06239018B1 Method for forming dielectric layers 有权
标题翻译：电介质层形成方法
公开(公告)号：US06239018B1
公开(公告)日：2001-05-29
申请号：US09241326
申请日：1999-02-01
申请人： Chih-Chien Liu , Juan-Yuan Wu , Water Lur
发明人： Chih-Chien Liu , Juan-Yuan Wu , Water Lur
IPC分类号： H01L21316
CPC分类号： H01L21/02112 , C23C16/50 , H01L21/02107 , H01L21/02274 , H01L21/02304 , H01L21/31612
摘要： A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
摘要翻译：描述形成电介质层的方法。配线在所提供的半导体衬底上形成。间隔件形成在布线的侧壁上。通过第一HDPCVD步骤，例如无偏压，未夹紧的HDPCVD，在布线和间隔物上形成衬垫层。在衬垫层上形成介电层以覆盖布线，并通过第二HDPCVD步骤填充布线之间的间隙。

80. 发明授权

US06214691B1 Method for forming shallow trench isolation 失效
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06214691B1
公开(公告)日：2001-04-10
申请号：US09228932
申请日：1999-01-12
申请人： Gwo-Shii Yong , Chih-Chien Liu , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yong , Chih-Chien Liu , Tri-Rung Yew , Water Lur
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.
摘要翻译：公开了一种用于形成浅沟槽隔离的方法。该方法包括在半导体衬底中形成沟槽，然后通过等离子体工艺在半导体衬底上覆盖氧化硅层，从而基本上重新填充沟槽。此后，在等离子体沉积的氧化硅层上形成光致抗蚀剂层，然后蚀刻光致抗蚀剂层的一部分。然后等离子体沉积的氧化硅层被各向同性地蚀刻，然后最终去除光致抗蚀剂层。

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