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71. 发明授权

US06673401B2 Nanoparticle structures utilizing synthetic DNA lattices 有权
标题翻译：利用合成DNA晶格的纳米颗粒结构
公开(公告)号：US06673401B2
公开(公告)日：2004-01-06
申请号：US09733968
申请日：2000-12-12
申请人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
发明人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
IPC分类号： B32B1102
CPC分类号： B82Y25/00 , C07B2200/01 , C12N15/10 , C40B40/00 , H01F1/0054 , H01F1/0063 , Y10T428/13 , Y10T428/24331 , Y10T428/249978 , Y10T428/249979 , Y10T428/24999 , Y10T428/32
摘要： A laminar structure upon a substrate is formed from a) a lattice layer comprising DNA (deoxyribonucleic acid) segments arranged to form cells of the lattice layer, and b), at least one nanoparticle being disposed within each cell of the lattice layer. The nanoparticles are preferably of substantially uniform diameter not exceeding 50 nanometers. A coating may be applied to adhere the the particles to the substrate and to maintain their substantially uniform spaced-apart relationship. The DNA lattice layer is fabricated using known automated synthetis methods, and is designed to contain specific nucleotide base sequences which cause the DNA to form an ordered array of openings, or lattice cells, by self-assembly. Self-assembly of the DNA lattice may be at an air-liquid interface, or in solution. A preferred embodiment is a magnetic storage medium in which the particles are magnetic particles with diameters in the range of 5-20 nm., the particles being organized in square information bits with each bit holding of 4, 9, 16, 25 etc. particles to produce areal information storage densities on the order of 1000 gigabits (one terabit) per square inch. The lattice of bits may be stabilized and protected by a deposited thin film, hard, abrasion-resistant coating.
摘要翻译：基底上的层状结构由a）由布置成形成晶格层的单元的DNA（脱氧核糖核酸）区的晶格层形成，以及b）至少一个纳米颗粒设置在晶格层的每个单元内。纳米颗粒优选具有不超过50纳米的基本均匀的直径。可以施加涂层以将颗粒附着到基材上并保持其基本均匀的间隔关系。使用已知的自动化合成方法制造DNA晶格层，并且被设计为含有特定的核苷酸碱基序列，其通过自组装使DNA形成有序的开口阵列或晶格细胞。 DNA晶格的自组装可以在空气 - 液体界面处或在溶液中。优选的实施方案是磁性存储介质，其中颗粒是直径在5-20nm范围内的磁性颗粒，颗粒被组织成平方信息位，每个位保持4,9,16,25等颗粒以产生大约1000吉比特（1兆比特）每平方英寸的面积信息存储密度。位的晶格可以被沉积的薄膜，硬的耐磨涂层稳定和保护。

72. 发明授权

US06265021B1 Nanoparticle structures utilizing synthetic DNA lattices 失效
标题翻译：利用合成DNA晶格的纳米颗粒结构
公开(公告)号：US06265021B1
公开(公告)日：2001-07-24
申请号：US09127452
申请日：1998-07-31
申请人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
发明人： Charles T. Black , Stephen M. Gates , Christopher B. Murray , Shouheng Sun
IPC分类号： B32B1100
CPC分类号： B82Y25/00 , C07B2200/01 , C12N15/10 , C40B40/00 , H01F1/0054 , H01F1/0063 , Y10T428/13 , Y10T428/24331 , Y10T428/249978 , Y10T428/249979 , Y10T428/24999 , Y10T428/32
摘要： A laminar structure upon a substrate is formed from a) a lattice layer comprising DNA (deoxyribonucleic acid) segments arranged to form cells of the lattice layer, and b), at least one nanoparticle being disposed within each cell of the lattice layer. The nanoparticles are preferably of substantially uniform diameter not exceeding 50 nanometers. A coating may be applied to adhere the particles to the substrate and to maintain their substantially uniform spaced-apart relationship. The DNA lattice layer is fabricated using known automated synthetis methods, and is designed to contain specific nucleotide base sequences which cause the DNA to form an ordered array of openings, or lattice cells, by self-assembly. Self-assembly of the DNA lattice may be at an air-liquid interface, or in solution. A preferred embodiment is a magnetic storage medium in which the particles are magnetic particles with diameters in the range of 5-20 nm., the particles being organized in square information bits with each bit holding of 4, 9, 16, 25 etc. particles to produce real information storage densities on the order of 1000 gigabits (one terabit) per square inch. The lattice of bits may be stabilized and protected by a deposited thin film, hard, abrasion-resistant coating.
摘要翻译：基底上的层状结构由a）由布置成形成晶格层的单元的DNA（脱氧核糖核酸）区的晶格层形成，以及b）至少一个纳米颗粒设置在晶格层的每个单元内。纳米颗粒优选具有不超过50纳米的基本均匀的直径。可以施加涂层以将颗粒附着到基底上并保持其基本均匀的间隔关系。使用已知的自动化合成方法制造DNA晶格层，并且被设计为含有特定的核苷酸碱基序列，其通过自组装使DNA形成有序的开口阵列或晶格细胞。 DNA晶格的自组装可以在空气 - 液体界面处或在溶液中。优选的实施方案是磁性存储介质，其中颗粒是直径在5-20nm范围内的磁性颗粒，颗粒被组织成平方信息位，每个位保持4,9,16,25等颗粒以产生大约1000吉比特（1兆比特）每平方英寸的真实信息存储密度。位的晶格可以被沉积的薄膜，硬的耐磨涂层稳定和保护。

73. 发明授权

US4794863A Motive structure for transporting workpieces 失效
标题翻译：运输工件的动力结构
公开(公告)号：US4794863A
公开(公告)日：1989-01-03
申请号：US171320
申请日：1988-03-21
申请人： Stephen M. Gates , Michael Liehr , Michel G. E. G. Renier , Gary W. Rubloff
发明人： Stephen M. Gates , Michael Liehr , Michel G. E. G. Renier , Gary W. Rubloff
IPC分类号： B23P19/00 , B23Q7/00 , B61D47/00 , B65G25/02 , B65G35/06 , B65G47/52 , B65G49/07 , B61B13/00
CPC分类号： B65G25/02
摘要： An improved motive structure for transporting workpieces (wafers, chip, packages, etc.) between processing stations or tools in a manufacturing operation. The structure includes a first circular crankshaft assembly connected to center axles disposed at right angles to the transport motion. A second such crankshaft assembly is located some distance along the path of motion. Three driverods are connected between the first and second crankshaft assemblies, each affixed 120.degree. apart on the circular crankshafts so that each driverod is moved upward, then forward along the transport direction, then downward and backward to its original position as the crankshafts go through a complete 360.degree. rotation. The structure is disposed beneath transport rails which hold movable containers for holding the workpieces. As a driverod moves up and forward, it contacts a spring-loaded element on the movable container and drives it forward by friction contact. As each driverod begins to move down and away from the workpiece container, the next driverod is being rotated up and forward to continue to move the container along the rails. Pluralities of such structures are linearly arranged to provide an extended transport system.

74. 发明授权

US08759976B2 Structure with sub-lithographic random conductors as a physical unclonable function 有权
标题翻译：具有亚光刻随机导体作为物理不可克隆功能的结构
公开(公告)号：US08759976B2
公开(公告)日：2014-06-24
申请号：US13570972
申请日：2012-08-09
申请人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
发明人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
IPC分类号： H01L23/485
CPC分类号： H01L23/5228 , H01L21/0332 , H01L21/32139 , H01L23/52 , H01L23/522 , H01L23/576 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H01L2924/00
摘要： A secure electronic structure including a plurality of sub-lithographic conductor features having non-repeating random shapes as a physical unclonable function (PUF) and an integrated circuit including the same are provided. Some of the conductor features of the plurality of conductor features form ohmic electrical contact to a fraction of regularly spaced array of conductors that are located above or beneath the plurality of conductor features having the non-repeating shapes, while other conductor features of the plurality of conductor features do not form ohmic electrical contact with any of the regularly spaced array of conductors. Thus, a unique signature of electrical continuity is provided which can be used as a PUF within an integrated circuit.
摘要翻译：提供一种包括具有非重复随机形状作为物理不可克隆功能（PUF）的多个亚光刻导体特征的安全电子结构以及包括该非亚光刻导体特征的集成电路。多个导体特征中的一些导体特征形成欧姆电接触到位于具有非重复形状的多个导体特征的上方或下方的规则间隔的导体阵列的一部分，而多个导体特征的其它导体特征导体特征不与任何规则间隔的导体阵列形成欧姆电接触。因此，提供了可以在集成电路内用作PUF的电连续性的唯一签名。

75. 发明申请

US20140042627A1 ELECTRONIC STRUCTURE CONTAINING A VIA ARRAY AS A PHYSICAL UNCLONABLE FUNCTION 审中-公开
标题翻译：通过阵列的电子结构作为物理不可靠的功能
公开(公告)号：US20140042627A1
公开(公告)日：2014-02-13
申请号：US13570968
申请日：2012-08-09
申请人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
发明人： Daniel C. Edelstein , Gregory M. Fritz , Stephen M. Gates , Dirk Pfeiffer
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/57 , G06F21/73 , G09C1/00 , H01L21/0332 , H01L21/31144 , H01L21/76816 , H01L21/76847 , H01L21/76877 , H01L23/5226 , H01L23/5228 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H01L2924/00
摘要： A secure electronic structure is provided including a via array as a physical unclonable function (PUF). Specifically, the secure electronic structure includes an array of electrical contact vias located between a lower level of a first regularly spaced array of conductors and an upper level of a second regularly spaced array of conductors. Each electrical contact via of the via array is individually addressed through the first regularly spaced array of conductors in the lower level and the second regularly spaced array of conductors in the upper level and has a resistance value. Each resistance value of each electrical contact via forms a distribution of resistance values, wherein the distribution of resistance values is random. This random distribution of the resistance values of the array of electrical contact vias can be used as a physical unclonable function in the electronic structure of the present disclosure.
摘要翻译：提供了一种安全的电子结构，其包括作为物理不可克隆功能（PUF）的通孔阵列。具体地，安全电子结构包括位于第一规则间隔的导体阵列的较低电平和第二规则间隔的导体阵列的较高电平之间的电接触通孔的阵列。通孔阵列的每个电接触通孔通过下层中的第一规则间隔的导体阵列和上层中的第二规则间隔的导体阵列单独寻址，并且具有电阻值。每个电接触通孔的每个电阻值形成电阻值的分布，其中电阻值的分布是随机的。电接触通孔阵列的电阻值的这种随机分布可以用作本公开的电子结构中的物理不可克隆功能。

76. 发明授权

US08525169B1 Reliable physical unclonable function for device authentication 有权
标题翻译：用于设备认证的可靠的物理不可克隆功能
公开(公告)号：US08525169B1
公开(公告)日：2013-09-03
申请号：US13572289
申请日：2012-08-10
申请人： Daniel C. Edelstein , Stephen M. Gates , Edward W. Kiewra , Satyanarayana V. Nitta , Ramachandran Muralidhar , Dirk Pfeiffer
发明人： Daniel C. Edelstein , Stephen M. Gates , Edward W. Kiewra , Satyanarayana V. Nitta , Ramachandran Muralidhar , Dirk Pfeiffer
IPC分类号： H01L21/66 , H01L21/74
CPC分类号： H01L23/544 , H01L21/268 , H01L21/76894 , H01L22/14 , H01L23/5226 , H01L23/53271 , H01L23/573 , H01L2223/5444 , H01L2223/5448 , H01L2924/0002 , H04L9/3247 , H04L9/3278 , H01L2924/00
摘要： The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.
摘要翻译：本公开涉及具有物理不可克隆功能的安全装置。该器件包括在集成电路的后端中的至少一个通孔中具有半导体材料的集成电路。本公开还涉及一种用于制造具有物理不可克隆功能的安全装置的方法。该方法包括提供集成电路并将集成电路的后端中的至少一个通孔添加半导体材料。在一些情况下，测量至少一个通孔中的半导体材料的特性以导出签名。

77. 发明授权

US08440999B2 Semiconductor chip with graphene based devices in an interconnect structure of the chip 有权
标题翻译：半导体芯片采用基于石墨烯的器件，在芯片的互连结构中
公开(公告)号：US08440999B2
公开(公告)日：2013-05-14
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
IPC分类号： H01L29/78
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译：半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。第二电介质材料包括其中包含的至少一个第二导电区域，并且所述至少一个第二导电区域与所述至少一个含石墨烯的半导体器件的导电元件接触。

78. 发明申请

US20120306017A1 WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS 有权
标题翻译：基于可重构互连网络的场效应设备的接线开关设计
公开(公告)号：US20120306017A1
公开(公告)日：2012-12-06
申请号：US13479946
申请日：2012-05-24
申请人： Daniel C. Edelstein , Stephen M. Gates , Ramachandran Muralidhar , Thomas N. Theis
发明人： Daniel C. Edelstein , Stephen M. Gates , Ramachandran Muralidhar , Thomas N. Theis
IPC分类号： H01L21/20 , H01L29/78
CPC分类号： H01L23/525 , H01L27/124 , H01L2924/0002 , H03K19/1736 , H01L2924/00
摘要： An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET).
摘要翻译：一种集成电路，包括基板，设置在基板上方的至少一个金属布线层。金属布线层包括布线开关和多个图案化导体。布线开关包括背栅场效应晶体管（BGFET）。

79. 发明授权

US08276018B2 Non-volatile memory based reliability and availability mechanisms for a computing device 有权
标题翻译：用于计算设备的基于非易失性存储器的可靠性和可用性机制
公开(公告)号：US08276018B2
公开(公告)日：2012-09-25
申请号：US12771293
申请日：2010-04-30
申请人： Eren Kursun , Philip G. Emma , Stephen M. Gates
发明人： Eren Kursun , Philip G. Emma , Stephen M. Gates
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F11/0724 , G06F11/0787 , G06F11/0793
摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.
摘要翻译：提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。

80. 发明申请

US20120032311A1 MULTI COMPONENT DIELECTRIC LAYER 有权
标题翻译：多组分电介质层
公开(公告)号：US20120032311A1
公开(公告)日：2012-02-09
申请号：US12853278
申请日：2010-08-09
申请人： Stephen M. Gates , Alfred Grill , Son V. Nguyen , Satyanarayana V. Nitta
发明人： Stephen M. Gates , Alfred Grill , Son V. Nguyen , Satyanarayana V. Nitta
IPC分类号： H01L29/06 , H01L23/538 , H01L21/314
CPC分类号： H01L29/06 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L23/538 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.
摘要翻译：描述了一种原位方法，其包括等离子体增强化学气相沉积，其包括流动含有Si，Si + C，B，Si + B，Si + B + C和B + C的前体中的至少一种和含N前体并且第二次除去N前体，并开始将氧化剂气体和致孔剂气体流入室中。描述了一种介电层，其包括在整个网络中具有无机随机三维共价键的网络，其包含至少一种SiCN，SiCNH，SiN，SiNH，BN，BNH，CBN，CBNH，BSiN，BSiNH，SiCBN和SiCBNH作为第一组分和作为与其相邻的第二组分的低k电介质。

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