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    • 72. 发明申请
    • Convergence compensating deflection yoke
    • 会聚补偿偏转线圈
    • US20050052111A1
    • 2005-03-10
    • US10891432
    • 2004-07-13
    • Jae HanJong ParkJae Song
    • Jae HanJong ParkJae Song
    • H01J29/70H01J29/76H01J29/46
    • H01J29/703H01J29/762H01J2229/5684
    • The present invention relates to a deflection yoke which includes an iron plate on a neck portion of a coil separator to convert PQH from a negative tendency to a positive one so that degradation of convergence features can be prevented. The deflection yoke of the invention comprises: a coil separator including a screen portion coupled to a screen panel of a CRT, a rear cover, and a neck portion extended from the central plane of the rear cover to be coupled to an electron gun portion of the CRT; horizontal and vertical deflection coils provided in the inner and outer sides of the coil separator to form horizontal and vertical deflection magnetic fields to control an electron beam; and compensating means provided in the neck portion of the coil separator to compensate convergence on a screen. The negative tendency of PQH according to the flattening of the CRT can be changed into the positive tendency by providing the compensating iron plates in the rear plate side of the coil separator in the shape of wrapping the neck portion.
    • 偏转线圈技术领域本发明涉及一种偏转线圈,其包括在线圈分离器的颈部上的铁板,以将PQH从负趋势转换为正向,从而可以防止会聚特征的退化。 本发明的偏转线圈包括:线圈分离器,其包括耦合到CRT的屏幕面板的屏幕部分,后盖和从后盖的中心平面延伸的颈部,以连接到电子枪部分的电子枪部分 CRT; 设置在线圈分离器的内侧和外侧的水平和垂直偏转线圈,以形成水平和垂直偏转磁场,以控制电子束; 以及设置在线圈分离器的颈部中以补偿屏幕上的会聚的补偿装置。 通过在线圈分离器的后板侧设置以包裹颈部的形状的补偿铁板,可以将根据CRT的扁平化的PQH的消极趋势变为积极的趋势。
    • 76. 发明授权
    • Voltage generator to compensate sense amplifier trip point over temperature in non-volatile memory
    • 电压发生器补偿非易失性存储器中读出放大器跳变点温度过高
    • US07974134B2
    • 2011-07-05
    • US12617860
    • 2009-11-13
    • Fanglin ZhangJong ParkMan MuiAlexander ChuSeungpil Lee
    • Fanglin ZhangJong ParkMan MuiAlexander ChuSeungpil Lee
    • G11C16/06
    • G11C16/26G11C11/5642
    • In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.
    • 在非易失性存储器系统中,电压发生器向用于感测电路的电压设置晶体管的栅极提供电压,以在感测节点处设置初始电压。 在感测周期结束时,将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。 为了解决温度变化和制造工艺变化,电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。 结果,即使初始电压和跳变点变化,初始电压和跳闸点之间的电压摆动也是恒定的。 在特定实施方案中,电压发生器使用共源共栅电流镜电路,并从带隙电压电路接收参考电流。
    • 77. 发明申请
    • High-Voltage Nmos-Transistor and Associated Production Method
    • 高电压晶体管及相关生产方法
    • US20070278570A1
    • 2007-12-06
    • US11659512
    • 2005-08-05
    • Martin KnaippJong Park
    • Martin KnaippJong Park
    • H01L29/78H01L21/336
    • H01L29/66681H01L29/0634H01L29/0878H01L29/1095H01L29/42368H01L29/7816
    • An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.
    • 深导电阱(DP)中的n导电掺杂源区(2),沟道区(13),由反掺杂区(12)形成的漂移区(14),优选地在栅极场板 6),栅极氧化物(8)绝缘,并且布置在深导电阱(DN)中的n导电掺杂漏极区域(3)依次布置在衬底(1)的顶侧。 深沟道阱(DP)和深导通阱(DN)之间的横向结(11)存在于漏极区域(3)附近的漂移路径(14)中,以避免 在晶体管工作期间,沟道区域(13)中的高电压降,以及在源极和漏极之间实现高阈值电压以及高的击穿电压。
    • 78. 发明申请
    • Non-Volatile Semiconductor Memory Devices with Lower and Upper Bit Lines Sharing a Voltage Control Block, and Memory Cards and Systems Having the Same
    • 具有下位线和上位线的非易失性半导体存储器件共享电压控制块,以及具有相同功能的存储卡和系统
    • US20070242512A1
    • 2007-10-18
    • US11764352
    • 2007-06-18
    • Jong ParkMin Park
    • Jong ParkMin Park
    • G11C16/24
    • G11C11/5628G11C16/0483
    • A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.
    • 一种非易失性半导体存储器件包括一个页缓冲器,包括一个下锁存器块和一个上锁存器,以及一个存储器阵列,该存储器阵列经由下公共位线连接到下锁存器块,并经由下公共位线连接到上锁存器块 上位公用位线。 存储器阵列包括可选择地连接到下公共位线的多个非易失性存储器单元,较低偶数位线和下部奇数位线,可选择地连接的上部偶数位线和上部奇数位线 到所述上公共位线,响应于第一连接控制信号将所述下偶数位线电连接到所述上偶数位线的第一开关和将所述下奇数位线电连接到所述上奇数位线的第二开关 响应于第二连接控制信号。
    • 80. 发明申请
    • High frequency heat treatment method for fine bottom-closed hole
    • 高频热处理方法为细底孔封闭
    • US20070215603A1
    • 2007-09-20
    • US11418209
    • 2006-05-05
    • Jong ParkYoung Jeon
    • Jong ParkYoung Jeon
    • H05B6/02
    • H05B6/101H05B6/38
    • A high frequency heat treatment method for a fine bottom-closed hole comprises preparing a coil so as to be completely inserted into the fine bottom-closed hole, preparing a core for controlling a magnetic flux within the coil such that the core protrudes from upper and lower sides of the coil, heat-treating a target part of the fine bottom-closed hole under conditions of a heating time of 2˜3 seconds, an output power of 200˜300 kW, a quenching time of 3˜5 seconds, a positive electrode voltage of 4˜8 kV, and a positive electrode current of 2.0˜4.5 A, and quenching the heat-treated part of the fine bottom-closed hole with cooling nozzles fixed around the heat-treated part such that a sufficient amount of cooling water is injected uniformly over the whole heated part with a sufficient pressure via the cooling nozzles.
    • 精细底部闭孔的高频热处理方法包括:准备线圈以完全插入细底孔中,制备用于控制线圈内的磁通量的芯,使得芯从上方突出, 在线圈的下侧,加热时间为2〜3秒,输出功率为200〜300kW,淬火时间为3〜5秒的条件下,对细底孔的目标部分进行热处理,a 正电极电压为4〜8kV,正电极电流为2.0〜4.5A,用固定在热处理部件周围的冷却喷嘴淬火细底部封闭孔的热处理部分, 冷却水通过冷却喷嘴以足够的压力均匀地喷射在整个加热部件上。