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    • 71. 发明授权
    • Synchronizing method
    • 同步方法
    • US07394884B2
    • 2008-07-01
    • US10789546
    • 2004-02-27
    • Tarek KaylaniFang LuHenry Samueli
    • Tarek KaylaniFang LuHenry Samueli
    • H04L7/00G06F12/02
    • G06F5/14G06F1/025G06F5/12G06F2205/061G06F2205/126H03L7/07H03L7/081H03L7/085H03L7/0996H03L7/23H04J3/062
    • To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal. A phase locked loop that synchronizes the phase shifted signal generating oscillator to a frequency reference is nested in the control loop that selects one of the phase shifted signals as the output signal.
    • 为了使定期发生的脉冲串与聚束脉冲串的平均值同步,振荡器以给定频率产生多个不同的相移信号。 选择一个相移信号作为输出信号。 将输出信号与聚束脉冲串进行比较。 所选择的相移信号响应于比较而改变,因此输出信号以聚束脉冲串的平均频率发生。 振荡器形成为具有相同可控延迟的多个差分放大器级。 这些级连接在一起以形成环形振荡器。 输出信号通过FIFO与聚束脉冲序列进行比较。 代表FIFO状态的信号被用作误差信号,以控制用作输出信号的相移信号的选择。 将相移信号产生振荡器与频率基准同步的锁相环嵌套在选择相移信号之一作为输出信号的控制回路中。
    • 74. 发明申请
    • System and method for ESD protection
    • ESD保护的系统和方法
    • US20070007598A1
    • 2007-01-11
    • US11521361
    • 2006-09-15
    • Agnes WooKenneth KindsfaterFang Lu
    • Agnes WooKenneth KindsfaterFang Lu
    • H01L23/62
    • H01L23/50H01F17/0006H01F17/0013H01F2017/0053H01F2021/125H01L23/5227H01L23/60H01L27/0248H01L27/0251H01L27/08H01L2924/0002H01L2924/3011H03B5/1212H03B5/1228H03B5/1243H03B5/364H03D7/161H03D7/18H03G1/0029H03H11/1291H03J1/0075H03J3/04H03J3/08H03J3/185H03J2200/10H03L7/10H03L7/23H04B1/28H01L2924/00
    • An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
    • 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合,以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器,以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波,频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中,使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器,以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。
    • 78. 发明授权
    • Automatic BIOS recovery in a multi-node computer system
    • 多节点计算机系统中的自动BIOS恢复
    • US06934873B2
    • 2005-08-23
    • US10085915
    • 2002-02-28
    • Fang LuFrank L. Wu
    • Fang LuFrank L. Wu
    • H04L1/22G06F11/00
    • H04L1/22G06F11/1417
    • A method of recovering from basic input/output system (BIOS) corruption operates in a multi-node computer system (MCS). The MCS includes first and second nodes, a first firmware unit in the first node, and a second firmware unit in the second node. According to the method, in response to initiation of a boot sequence for the MCS, the MCS automatically checks a BIOS image in the first firmware unit in the first node for corruption. In response to detecting corruption of the BIOS image in the first firmware unit, the MCS automatically recovers from the corruption by causing a good BIOS image to be copied from the second firmware unit in the second node to the first firmware unit in the first node. In one example embodiment, the MCS may contain multiple nodes, and the MCS may automatically recover from BIOS errors if any node contains a good BIOS image.
    • 从基本输入/输出系统(BIOS)故障恢复的方法在多节点计算机系统(MCS)中运行。 MCS包括第一和第二节点,第一节点中的第一固件单元和第二节点中的第二固件单元。 根据该方法,响应于针对MCS的引导顺序的启动,MCS自动检查第一节点中的第一固件单元中的BIOS映像是否损坏。 响应于检测到第一固件单元中的BIOS映像的损坏,MCS通过使第二节点中的第二固件单元中的良好的BIOS映像复制到第一节点中的第一固件单元而自动从损坏中恢复。 在一个示例实施例中,MCS可以包含多个节点,并且如果任何节点包含良好的BIOS映像,则MCS可以自动从BIOS错误恢复。
    • 79. 发明授权
    • Apparatus for, and method of, processing signals transmitted over a local area network
    • 用于处理通过局域网传输的信号的装置和方法
    • US06459730B1
    • 2002-10-01
    • US09482699
    • 2000-01-13
    • Henry SamueliFang LuAvanindra Madisetti
    • Henry SamueliFang LuAvanindra Madisetti
    • H04L2701
    • H04L7/0054H04L7/0004H04L7/0334H04L25/03057H04L25/03885H04L25/062H04L2025/03503
    • Digital signals provided by a repeater connected to a plurality of clients by unshielded twisted wire pairs, are converted to analog signals which become degraded during transmission through the wires. Clients convert the degraded analog signals to digital signals. Digital signal phases are coarsely adjusted to have assumed zero crossing times coincide in-time with a clock signal zero crossing. Signal polarity, and the polarity of any change, is determined at the assumed zero crossing times of the digital signals. Pre-cursor and post-cursor responses, resulting from signal degradation, are respectively inhibited by a feed forward and a decision feedback equalizer. The time duration of post-cursor response is further inhibited by a high pass filter and a tail canceller. Phase adjustments are made, after response inhibition, by determining the polarity, and the polarity of any change, at the assumed zero crossing times. Before phase adjustments are made, a phase offset is provided in order to compensate for phase degradations introduced by the unshielded twisted wire pairs.
    • 由通过非屏蔽双绞线连接到多个客户端的中继器提供的数字信号被转换为在通过电线传输期间降级的模拟信号。 客户端将降级的模拟信号转换为数字信号。 数字信号相位粗略地调整为假定零交叉时间与时钟信号过零时间一致。 信号极性和任何变化的极性在假定的数字信号的零交叉时间确定。 分别由前馈和判决反馈均衡器阻止由信号劣化引起的前标和后视标响应。 后置光标响应的持续时间被高通滤波器和尾部消除器进一步抑制。 通过在假设的零交叉时间确定极性和任何变化的极性,在响应抑制之后进行相位调整。 在进行相位调整之前,提供相位偏移以补偿由未屏蔽的双绞线引入的相位劣化。