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71. 发明公开

KR1020160014195A 반도체 장치 및 이의 제조 방법 审中-实审
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020160014195A
公开(公告)日：2016-02-11
申请号：KR1020140095943
申请日：2014-07-28
申请人： 삼성전자주식회사
发明人： 박상진 , 백재직 , 송명근 , 윤보언 , 최석헌 , 한정남
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/66545 , H01L21/0228 , H01L21/31051 , H01L21/31111 , H01L21/76897 , H01L29/0847 , H01L29/165 , H01L29/4983 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L29/7811
摘要： 본발명은반도체장치및 이의제조방법에관한것으로, 보다구체적으로, 활성패턴이제공된기판; 상기활성패턴을가로지르는게이트전극; 및상기게이트전극상의게이트캡핑패턴을포함할수 있다. 이때, 상기게이트캡핑패턴의폭은상기게이트전극의폭보다크고, 상기게이트캡핑패턴은, 상기게이트전극의양 측벽들을덮으며상기기판을향하여연장된연장부를포함할수 있다.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。半导体器件包括：衬底，其包括有源图案; 穿过有源图案的栅电极; 和栅极电极上的栅极覆盖图案。此时，栅极覆盖图案的宽度比栅电极的宽度宽，并且栅极封盖图案包括覆盖栅电极的两个侧壁并朝向衬底延伸的延伸部分。因此，半导体器件包括具有更好的电性能的场效应晶体管。

72. 发明授权

KR101534678B1 텅스텐 콘택 플러그를 산소 분위기에서 ＲＴＡ 처리하고, ＲＴＯ 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법 有权
标题翻译：通过在氧气氛下快速退火钨接触塞并在氢气氛下还原RTO脉冲来制造半导体器件的方法
公开(公告)号：KR101534678B1
公开(公告)日：2015-07-08
申请号：KR1020090011506
申请日：2009-02-12
申请人： 삼성전자주식회사
发明人： 최석헌 , 홍창기 , 최재형 , 손윤호 , 박민영 , 탁용석
IPC分类号： H01L21/28 , H01L21/324
CPC分类号： H01L21/76877 , H01L21/321 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： 콘택홀에텅스텐을증착할때 텅스텐의그레인이 3방향에서진행되기때문에, 삼중점에서씸(Seam) 기타국부단차가발생한다. 콘택플러그에씸이존재하면, 텅스텐이열화되고수율이감소한다. 국부단차를개선하기위하여, 텅스텐이산소분위기에서고온으로가열되면부피가 2∼3배로팽창되는특성을이용한다. 텅스텐콘택플러그를고온의산소분위기에서히팅(Heating) 혹은플라즈마(Plasma) 방식으로급속열처리(RTA)하고, 층간절연막의표면위로부피팽창된텅스텐을버핑 CMP 공정을통하여제거한다. 또한, 텅스텐의산화공정에서콘택저항이증가되는점을개선하기위하여, 급속열산화(RTO) 및버핑연마처리된텅스텐콘택플러그를수소가스분위기에서급속열환원(RTH)시키며, 환원반응에의하여텅스텐옥사이드(WO)는순수텅스텐(W)으로전환된다.

73. 发明授权

KR101477661B1 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법 有权
标题翻译：无电触摸图案及其制造方法
公开(公告)号：KR101477661B1
公开(公告)日：2014-12-31
申请号：KR1020080069700
申请日：2008-07-17
申请人： 삼성전자주식회사
发明人： 최석헌 , 홍창기 , 손윤호 , 정주영
IPC分类号： H01L21/28 , H01L21/324
CPC分类号： H01L21/76888 , H01L21/76879 , H01L21/76883 , H01L27/24
摘要： 미세한홀 안에 seam 없는텅스텐플러그는상변화메모리디바이스형성시다이오드와하부전극간을연결하는통로가되어계면저항을낮추어소프트페일이없는상변화메모리를형성할 수있다.

74. 发明公开

KR1020140113244A 반도체 장치 및 그 제조 방법 审中-实审
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020140113244A
公开(公告)日：2014-09-24
申请号：KR1020130055150
申请日：2013-05-15
申请人： 삼성전자주식회사
发明人： 김진범 , 최석헌
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76 , H01L21/76224 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L21/02667 , H01L27/1211 , H01L29/7853
摘要： Provided are a semiconductor device and a fabricating method thereof. A method of fabricating the semiconductor device includes forming a gate line in a direction intersecting with a fin, on a substrate having the fin, conformally forming an amorphous material to cover the substrate, the fin, and the gate line, removing a part of the amorphous material, crystalizing the remaining amorphous material, changing a part of the remaining amorphous material into a polycrystalline material, and removing the polycrystalline material.
摘要翻译：提供一种半导体器件及其制造方法。一种制造半导体器件的方法包括：在具有翅片的方向上形成栅极线，在具有翅片的基板上，保形地形成非晶材料以覆盖基板，鳍片和栅极线，去除部分将剩余的非晶材料结晶化，将剩余的非晶材料的一部分改变为多晶材料，并除去多晶材料。

75. 发明公开

KR1020120102386A 금속성 스토리지 노드를 구비한 반도체 소자 제조방법. 审中-实审
标题翻译：制造具有金属存储编号的半导体器件的方法
公开(公告)号：KR1020120102386A
公开(公告)日：2012-09-18
申请号：KR1020110020515
申请日：2011-03-08
申请人： 삼성전자주식회사
发明人： 이몽섭 , 황인석 , 곽병용 , 최석헌 , 이상준
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/84 , H01L27/10855 , H01L28/65
摘要： PURPOSE: A method for manufacturing a semiconductor device including a metallic storage node is provided to increase the capacitance of a capacitor by forming the metallic storage node with an uneven surface. CONSTITUTION: A device isolation layer(13) is formed on a predetermined region of a semiconductor substrate(1) to limit an active region(10). A common drain region(17) and a pair of source regions(15,19) are formed by injecting impurity ions into the active region. A plurality of contact pads(23) are formed on a substrate including the common drain region and the source region. An insulation layer(25) is formed on the substrate with the contact pad. A bit line(27) is formed in the insulation layer.
摘要翻译：目的：提供一种用于制造包括金属存储节点的半导体器件的方法，以通过形成具有不平坦表面的金属存储节点来增加电容器的电容。构成：在半导体衬底（1）的预定区域上形成器件隔离层（13）以限制有源区（10）。通过将杂质离子注入有源区域来形成公共漏极区（17）和一对源极区（15,19）。在包括公共漏极区域和源极区域的衬底上形成多个接触焊盘（23）。在衬底上用接触垫形成绝缘层（25）。在绝缘层中形成位线（27）。

76. 发明公开

KR1020120088027A 가변 저항체를 포함하는 반도체 기억 소자 및 그 제조 방법 有权
标题翻译：具有可变电阻器的半导体器件及其制造方法
公开(公告)号：KR1020120088027A
公开(公告)日：2012-08-08
申请号：KR1020100100466
申请日：2010-10-14
申请人： 삼성전자주식회사
发明人： 최석헌 , 윤보언 , 안경진 , 윤두성
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1683
摘要： PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to prevent atoms inside a contact plug from moving by protecting a contact plug during a mold opening portion. CONSTITUTION: A substrate includes a first area(50) and a second area(60). A mold dielectric layer(130) is arranged on a front side of the substrate. A contact plug(140) is arranged in the contact hole passing through the mold dielectric layer within the first area. A variable resistor(155a) is arranged within a mold opening portion passing through the mold dielectric layer within the second area. An upper side of the contact plug is arranged on a level lower than or substantially equal to the upper side of the mold dielectric layer.
摘要翻译：目的：提供半导体存储器件及其制造方法，以通过在开模部分期间保护接触插塞来防止接触插塞内的原子移动。构成：衬底包括第一区域（50）和第二区域（60）。在基板的前侧设置有模具电介质层（130）。在通过第一区域内的模具电介质层的接触孔中布置有接触插头（140）。可变电阻器（155a）布置在通过第二区域内的模具电介质层的模具开口部分内。接触插塞的上侧布置在低于或基本上等于模具电介质层的上侧的水平面上。

77. 发明公开

KR1020100128219A 도전 구조물, 이의 형성 방법, 이를 포함하는 반도체 소자 및 그 제조 방법 有权
标题翻译：导电结构，其形成方法，具有导电结构的半导体器件和制造半导体器件的方法
公开(公告)号：KR1020100128219A
公开(公告)日：2010-12-07
申请号：KR1020090110694
申请日：2009-11-17
申请人： 삼성전자주식회사
发明人： 최석헌 , 김경현 , 김태현 , 배기호 , 홍의관
IPC分类号： H01L21/8247 , H01L21/28
摘要： PURPOSE: A conductive structure, a method for forming the same, a semiconductor device including the same, and a method for manufacturing the same are provided to regulate resistance values by including a highly integrated conductive structure. CONSTITUTION: An interlayer insulating film(52) including an opening part is formed on a substrate(50). A conductive region is exposed through the opening part. A part of a tungsten oxide pattern(60) is contained in the opening part. The tungsten oxide pattern is in connection with the conductive region. A tungsten pattern(58b) is in contact with the lower side of the tungsten oxide pattern.
摘要翻译：目的：提供导电结构，其形成方法，包括该导电结构的半导体器件及其制造方法，以通过包括高度集成的导电结构来调节电阻值。构成：在基板（50）上形成包括开口部的层间绝缘膜（52）。导电区域通过开口部分露出。氧化钨图案（60）的一部分被包含在开口部分中。氧化钨图案与导电区域连接。钨图案（58b）与氧化钨图案的下侧接触。

78. 发明公开

KR1020100111378A 콘택 플러그, 이를 포함하는 반도체 장치 및 이의 제조 방법 无效
标题翻译：接触片，具有该接触片的半导体器件及其制造方法
公开(公告)号：KR1020100111378A
公开(公告)日：2010-10-15
申请号：KR1020090029770
申请日：2009-04-07
申请人： 삼성전자주식회사
发明人： 양상렬 , 황기현 , 윤병문 , 강동조 , 김경석 , 최석헌 , 최시영
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L21/02172 , H01L21/28525 , H01L21/32055 , H01L21/76877
摘要： PURPOSE: The contact plug, and the semiconductor device including the same and manufacturing method thereof silver. CONSTITUTION: The contact plug, and the semiconductor device including the same and manufacturing method thereof silver. The first conductive film, and second conductive film is included. The first conductive film comprises poly-silicon it is formed on the sidewall of opening between the structure formed in the top of the substrate and the substrate(200).
摘要翻译：目的：接触插头及包括其的半导体器件及其制造方法。构成：接触插头和包括其的半导体器件及其制造方法。包括第一导电膜和第二导电膜。第一导电膜包括多晶硅，其形成在形成于基板顶部的结构与衬底（200）之间的开口侧壁上。

79. 发明公开

KR1020100104280A 저저항의 매립형 금속 게이트 전극 구조를 갖는 반도체 장치 및 그 제조 방법 有权
标题翻译：具有低电阻率金属门电极结构的半导体器件及其制造方法
公开(公告)号：KR1020100104280A
公开(公告)日：2010-09-29
申请号：KR1020090022597
申请日：2009-03-17
申请人： 삼성전자주식회사
发明人： 전인상 , 이시형 , 유종렬 , 신유균 , 최석헌
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L29/4236 , H01L21/67207 , H01L21/823437 , H01L21/823456 , H01L29/66621 , H01L29/78
摘要： PURPOSE: A semiconductor device with a low resistance buried metal gate structure and a forming method thereof are provided to minimize a unit cell by obtaining the semiconductor device with a high electric characteristic. CONSTITUTION: A semiconductor substrate(100) is divided into an active region and an inactive region by forming a device isolation layer. A recess hole is formed on the active region. A gate dielectric layer(120) is formed in the recess hole. A barrier metal layer is formed on the gate dielectric layer. A metal layer for forming a nucleus is formed on the barrier metal layer. The phase of the metal layer is changed to have a low resistance characteristic by thermally processing the metal layer for forming the nucleus. A bulk metal electrode is formed based on the metal layer for forming the phase changed metal layer for forming the nucleus.
摘要翻译：目的：提供具有低电阻掩埋金属栅极结构的半导体器件及其形成方法，以通过获得具有高电特性的半导体器件使单元电池最小化。构成：通过形成器件隔离层，将半导体衬底（100）分为有源区和非活性区。在活性区域上形成凹坑。在凹陷孔中形成栅介质层（120）。在栅介质层上形成阻挡金属层。在阻挡金属层上形成用于形成核的金属层。金属层的相位通过热处理用于形成核的金属层而具有低电阻特性。基于形成用于形成核的相变金属层的金属层形成体金属电极。

80. 发明公开

KR1020100026049A 비휘발성 메모리 소자 및 그의 제조방법 无效
标题翻译：非易失性存储器件及其方法
公开(公告)号：KR1020100026049A
公开(公告)日：2010-03-10
申请号：KR1020080084871
申请日：2008-08-29
申请人： 삼성전자주식회사
发明人： 최석헌 , 김익수 , 정주영 , 홍창기
IPC分类号： H01L21/8242 , H01L27/108
摘要： PURPOSE: A non-volatile memory device and a manufacturing method thereof are provided to improve productivity by forming a protrusion plug formed by a rapid thermal annealing method on a contact plug exposed by an interlayer insulating film. CONSTITUTION: A transistor is formed on a substrate(10). An interlayer insulating film includes a contact hole selectively exposing the substrate corresponding to the source/drain region of the transistor. A contact plug(36) is formed inside the contact hole. A protrusion plug(38) which is highly protruded than the height of the interlayer insulating layer in the upper part of the contact plug is formed. A capacitor(46) composing of a bottom electrode(40) protruding to the interlayer insulating layer, a ferroelectric, and an upper electrode is formed in the upper part of the protruded plug. The protruded plug is formed by rapid thermal annealing for the contact plug formed in the contact hole.
摘要翻译：目的：提供一种非易失性存储器件及其制造方法，以通过在由层间绝缘膜暴露的接触插塞上形成由快速热退火法形成的突起塞来提高生产率。构成：晶体管形成在衬底（10）上。层间绝缘膜包括选择性地暴露与晶体管的源/漏区对应的衬底的接触孔。接触插塞（36）形成在接触孔内部。形成了比接触插塞的上部的层间绝缘层的高度高出突出的突起插塞（38）。在突出的插塞的上部形成有由突出到层间绝缘层的底部电极（40），铁电体和上部电极构成的电容器（46）。通过对形成在接触孔中的接触塞进行快速热退火而形成突出塞。

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