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71. 发明授权

US08569152B1 Cut-very-last dual-epi flow 有权
标题翻译：切割最后的双面流
公开(公告)号：US08569152B1
公开(公告)日：2013-10-29
申请号：US13487413
申请日：2012-06-04
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

72. 发明授权

US08557657B1 Retrograde substrate for deep trench capacitors 有权
标题翻译：深沟槽电容器逆行衬底
公开(公告)号：US08557657B1
公开(公告)日：2013-10-15
申请号：US13475485
申请日：2012-05-18
申请人： Veeraraghavan S. Basker , Wilfried E. Haensch , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Wilfried E. Haensch , Effendi Leobandung , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/0629 , H01L21/84 , H01L21/845 , H01L27/0248 , H01L27/0255 , H01L27/10826 , H01L27/1087 , H01L27/10879 , H01L27/10894 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L31/112
摘要： A semiconductor device includes a substrate having a first doped portion to a first depth and a second doped portion below the first depth. A deep trench capacitor is formed in the substrate and extends below the first depth. The deep trench capacitor has a buried plate that includes a dopant type forming an electrically conductive connection with second doped portion of the substrate and being electrically insulated from the first doped portion.
摘要翻译：半导体器件包括具有第一深度的第一掺杂部分和低于第一深度的第二掺杂部分的衬底。深沟槽电容器形成在衬底中并在第一深度之下延伸。深沟槽电容器具有掩埋板，该掩埋板包括与衬底的第二掺杂部分形成导电连接并与第一掺杂部分电绝缘的掺杂剂类型。

73. 发明授权

US08513073B1 Silicon germanium channel with silicon buffer regions for fin field effect transistor device 有权
标题翻译：具有硅缓冲区的硅锗通道用于鳍式场效应晶体管器件
公开(公告)号：US08513073B1
公开(公告)日：2013-08-20
申请号：US13600625
申请日：2012-08-31
申请人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chun Yeh
发明人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chun Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545
摘要： A method of forming a fin field effect transistor (finFET) device includes forming a silicon fin on a substrate; forming an inner spacer adjacent to a first portion of the silicon fin; forming silicon germanium regions adjacent to a second portion of the silicon fin and the inner spacer; and oxidizing the silicon germanium regions, such that the second portion of the silicon fin that is located adjacent to the silicon germanium regions is converted to a silicon germanium channel region during oxidizing of the silicon germanium regions, and such that the first portion of the silicon fin is protected by the inner spacer during oxidation of the silicon germanium regions, wherein the first portion of the silicon fin comprises a silicon buffer region located between the silicon germanium channel region and a source/drain region of the finFET device.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的方法包括在衬底上形成硅鳍片; 形成与所述硅片的第一部分相邻的内隔片; 形成与所述硅鳍片和所述内部间隔物的第二部分相邻的硅锗区域; 以及氧化硅锗区域，使得位于硅锗区附近的硅鳍片的第二部分在氧化硅锗区域期间被转换成硅锗沟道区，并且使硅的第一部分在硅锗区域的氧化期间，鳍片由内部间隔物保护，其中硅片的第一部分包括位于硅锗沟道区域和finFET器件的源极/漏极区域之间的硅缓冲区域。

74. 发明授权

US08507187B2 Multi-exposure lithography employing a single anti-reflective coating layer 失效
标题翻译：使用单个抗反射涂层的多曝光光刻
公开(公告)号：US08507187B2
公开(公告)日：2013-08-13
申请号：US12169888
申请日：2008-07-09
申请人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
发明人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F7/70466 , G03F7/70958 , H01L21/76816 , H01L21/76838 , Y10T428/24802
摘要： A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
摘要翻译：将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。施加第二光致抗蚀剂并将其图案化成具有接近最小特征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

75. 发明申请

US20130161744A1 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：US20130161744A1
公开(公告)日：2013-06-27
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

76. 发明授权

US08420464B2 Spacer as hard mask scheme for in-situ doping in CMOS finFETs 失效
标题翻译：隔膜作为CMOS finFET中原位掺杂的硬掩模方案
公开(公告)号：US08420464B2
公开(公告)日：2013-04-16
申请号：US13100589
申请日：2011-05-04
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Sivananda K. Kanakasabapathy , Hemant Adhikari
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.
摘要翻译：一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁结构体。在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。还描述了通过上述方法形成的结构。

77. 发明申请

US20130001789A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：US20130001789A1
公开(公告)日：2013-01-03
申请号：US13617060
申请日：2012-09-14
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith K. H. Wong
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

78. 发明申请

US20120318673A1 APPARATUS AND METHOD FOR ELECTROCHEMICAL PROCESSING OF THIN FILMS ON RESISTIVE SUBSTRATES 审中-公开
标题翻译：电阻基片薄膜电化学处理装置及方法
公开(公告)号：US20120318673A1
公开(公告)日：2012-12-20
申请号：US13596641
申请日：2012-08-28
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Matteo Flotta
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Matteo Flotta
IPC分类号： C25D7/12 , C25D17/00 , C25F7/00 , C25D11/02 , C25F3/02
CPC分类号： C25D5/54 , C25D5/006 , C25D5/02 , C25D7/123 , C25D11/005 , C25D11/024 , C25D17/001 , C25F3/14 , H01L21/28079 , H01L21/2885
摘要： An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
摘要翻译：一种电化学方法，包括：提供与导电表面电接触的125mm或更大的半导体晶片，其中所述半导体晶片的至少一部分与电解液接触，所述半导体晶片用作第一电极; 在所述电解液中提供第二电极，所述第一和第二电极连接到电源的相对端; 并且在第一和第二电极之间施加用作为电流的光源照射半导体晶片的表面。本发明还涉及一种包括光源和用于进行电化学过程的电化学组分的设备。

79. 发明授权

US08288276B2 Method of forming an interconnect structure including a metallic interfacial layer located at a bottom via portion 有权
标题翻译：形成包括位于底部通孔部分的金属界面层的互连结构的方法
公开(公告)号：US08288276B2
公开(公告)日：2012-10-16
申请号：US12346040
申请日：2008-12-30
申请人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Veeraraghavan S. Basker , William Tonti , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

80. 发明申请

US20110227165A1 HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
公开(公告)号：US20110227165A1
公开(公告)日：2011-09-22
申请号：US13151525
申请日：2011-06-02
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

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