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71. 发明授权

US07237991B2 Machine tool 有权
标题翻译：机床
公开(公告)号：US07237991B2
公开(公告)日：2007-07-03
申请号：US10891495
申请日：2004-07-15
申请人： Kazuyuki Hiramoto , Akihiro Mochizuki , Shunsuke Nakazawa , Satoshi Matsui
发明人： Kazuyuki Hiramoto , Akihiro Mochizuki , Shunsuke Nakazawa , Satoshi Matsui
IPC分类号： B23C1/06
CPC分类号： B23Q1/015 , B23Q5/40 , B23Q11/0032 , Y10T409/306776 , Y10T409/307728 , Y10T409/309576 , Y10T409/3098
摘要： The present invention provides a machine tool capable of reducing residual vibration occurring at the location time, thereby achieving responsiveness to a recent demand for higher acceleration/deceleration speed. The machine tool is configured such that a column 3 is fixed on a bed 2, a spindle head 6 for supporting a spindle 7 is disposed on a front face 3b′ of the column 3 to be movable in a Z-axis direction, and a pair of right and left Z-axis ball screws (spindle drive shafts) 22 for driving the vicinity of the gravity center of the spindle head 6 is disposed on the front face 3b′ of the column 3 to be symmetrical to each other with respect to a plane that includes an axis C of the spindle head 6 and is parallel to a Y axis, thereby driving the vicinity of the gravity center of the spindle head 6.
摘要翻译：本发明提供一种能够减少在定位时间发生的残余振动的机床，从而实现对最近对较高加速/减速速度的需求的响应。该机床被配置为使得柱3固定在床2上，用于支撑主轴7的主轴头6设置在柱3的前表面3b'上以能够在Z轴方向上移动，并且用于驱动主轴头6的重心附近的一对左，右Z轴滚珠丝杠（主轴驱动轴）22设置在柱3的前表面3b'上，以彼此对称地与相对于包括主轴头6的轴线C并平行于Y轴的平面，从而驱动主轴头6的重心附近。

72. 发明授权

US07122912B2 Chip and multi-chip semiconductor device using thereof and method for manufacturing same 失效
标题翻译：使用其的芯片和多芯片半导体器件及其制造方法
公开(公告)号：US07122912B2
公开(公告)日：2006-10-17
申请号：US11041241
申请日：2005-01-25
申请人： Satoshi Matsui
发明人： Satoshi Matsui
IPC分类号： H01L23/544 , H01L23/02
CPC分类号： H01L25/50 , H01L23/481 , H01L23/49827 , H01L23/49833 , H01L23/544 , H01L24/81 , H01L25/0657 , H01L2223/54473 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/81136 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , Y10S438/975 , H01L2924/00 , H01L2924/00014
摘要： The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, without adding any dedicated process step to the formation process for the marking for alignment. In the chip for the multi-chip semiconductor device having two or more electroconductive through plug in one chip for the multi-chip semiconductor device, one or more electroconductive through plugs are employed for the marking for alignment, and the chip is configured to allow identification of the marking for alignment on the front surface and/or the back surface of the chip for the multi-chip semiconductor device. Then, an insulating film is provided on the front surface and/or the back surface of the electrically conducting through plug.
摘要翻译：仅通过从芯片的前表面（光刻，蚀刻）的处理及其制造方法的仅在芯片的前表面和/或后表面上形成的用于对准的标记的多芯片半导体器件的芯片而不需要为对准标记的形成过程添加任何专门的工艺步骤。在具有用于多芯片半导体器件的一个芯片中具有两个或多个导电贯穿插头的多芯片半导体器件的芯片中，采用一个或多个导电通孔用于对准的标记，并且芯片被配置为允许识别用于在用于多芯片半导体器件的芯片的前表面和/或背表面上对准的标记。然后，在导电贯通插头的前表面和/或后表面上设置绝缘膜。

73. 发明申请

US20060143889A1 Machine tool 有权
标题翻译：机床
公开(公告)号：US20060143889A1
公开(公告)日：2006-07-06
申请号：US11366576
申请日：2006-03-03
申请人： Kazuyuki Hiramoto , Akihiro Mochizuki , Shunsuke Nakazawa , Satoshi Matsui
发明人： Kazuyuki Hiramoto , Akihiro Mochizuki , Shunsuke Nakazawa , Satoshi Matsui
IPC分类号： B23C9/00
CPC分类号： B23Q1/012 , B23Q1/015 , B23Q3/157 , B23Q3/15713 , B23Q3/15766 , Y10T29/5196 , Y10T408/91 , Y10T409/30532 , Y10T409/306048 , Y10T409/307728 , Y10T409/308288 , Y10T409/309576 , Y10T483/1733 , Y10T483/1748 , Y10T483/1752 , Y10T483/1755 , Y10T483/1757 , Y10T483/176
摘要： The present invention provides a machine tool capable of enhancing approachability to a spindle to improve work efficiency even when it includes a workpiece changer. The present invention includes: a bed 2; a saddle 4 disposed on the bed 2 to be movable in a forward and backward (Y-axis) direction in a front view of the machine tool 1; a table 5 disposed on the saddle 4 to be movable in a right and left (X-axis) direction; a column 3 having a shape of a gate bridged over a travel range of the table 5 and fixed on the bed 2; a spindle head 6 disposed on the column 3 to support a spindle 7 and movable in a vertical (Z-axis) direction; a workpiece changer 12 that turns a workpiece together with a pallet P or turns the workpiece independently, for workpiece replacement, between a workpiece standby position B set on a back face side of the bed 2 and the table 5 placed at a workpiece change position C, the workpiece changer 12 being disposed so as to set the workpiece change position C at a position under the column 3.
摘要翻译：本发明提供了一种能够提高对主轴的接近性的机床，即使在包括工件更换器时也能提高工作效率。本发明包括：床2; 设置在床2上的鞍座4能够在机床1的前视图中沿前后方向（Y轴）方向移动; 设置在鞍座4上的可沿左右（X轴）方向移动的工作台5; 柱3，其具有桥接在台子5的行进范围上并固定在床2上的门的形状; 主轴头6，其设置在柱3上，以支撑主轴7并且能够沿垂直（Z轴）方向移动; 工件更换器12，其将工件与托盘P一起旋转，或者在床2的背面侧的工件备用位置B与放置在工件变更位置C的工作台5之间独立地转动工件进行工件更换工件更换器12被设置成将工件变化位置C设置在柱3下方的位置。

74. 发明授权

US07012454B2 Clock shift circuit for gradual frequency change 有权
标题翻译：时钟移位电路，用于逐渐变频
公开(公告)号：US07012454B2
公开(公告)日：2006-03-14
申请号：US10796005
申请日：2004-03-10
申请人： Satoshi Matsui , Yukihiro Ozawa , Seiji Suetake
发明人： Satoshi Matsui , Yukihiro Ozawa , Seiji Suetake
IPC分类号： H03B19/00
CPC分类号： G06F1/08
摘要： A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.
摘要翻译：用于改变时钟的电路包括：时钟发生电路，其通过控制原始时钟信号的频率来产生输出时钟信号;以及控制电路，其响应于指示从a的变化的操作模式改变信号控制时钟发生电路第一操作模式转换为基于输出时钟信号工作的外部电路的第二操作模式，从而将对应于第一操作模式的第一频率的输出时钟信号改变为中间频率，然后从中间频率改变为第二频率对应于第二操作模式，中间频率具有在第一频率和第三频率之间的频率。

75. 发明申请

US20050121802A1 Offset-bonded, multi-chip semiconductor device 失效
标题翻译：偏移式多芯片半导体器件
公开(公告)号：US20050121802A1
公开(公告)日：2005-06-09
申请号：US10995491
申请日：2004-11-24
申请人： Masaya Kawano , Satoshi Matsui
发明人： Masaya Kawano , Satoshi Matsui
IPC分类号： H01L25/18 , H01L23/50 , H01L25/00 , H01L25/065 , H01L25/07 , H01L29/40
CPC分类号： H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.
摘要翻译：本发明的目的在于通过将上芯片与下芯片相抵消，以高可靠性的方式将下芯片和上芯片焊接在一起，同时确保足够的外部连接端子区域。基板2在其一个表面上具有凸块1，并且具有安装在其另一个表面上的第一芯片3。第二芯片4通过凸块5,6接合到第一芯片3，同时平行地将第二芯片4与第一芯片3抵消。在第一芯片3和第二芯片4的接合状态下，第一芯片3的一部分和第二芯片4的一部分重叠而不对准两者的中心。第二芯片4的重心落在由第一芯片3和第二芯片4之间的最外侧的凸块包围的区域内。

76. 发明授权

US5539900A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US5539900A
公开(公告)日：1996-07-23
申请号：US224682
申请日：1994-04-07
申请人： Satoshi Matsui
发明人： Satoshi Matsui
IPC分类号： G06F7/00 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/00 , G06F13/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/30174 , G06F9/30196 , G06F9/32 , G06F9/3822
摘要： An information processing system includes an instruction decoder part for decoding an external instruction signal and for outputting a control signal for executing an instruction based on a decoded result, and an operation part for carrying out an operation based on the control signal and for outputting an operation result. The operation part includes an operation unit which carries out an arithmetic logic operation and outputs the operation result, a flag register for holding states related to the operation result based on the control signal, and a buffer for successively holding predetermined states related to the operation result. The operation unit carries out the arithmetic logic operation by selectively reading the states held in the flag register and the buffer.
摘要翻译：一种信息处理系统，包括用于对外部指令信号进行解码并输出用于基于解码结果执行指令的控制信号的指令解码器部分，以及用于基于控制信号执行操作并用于输出操作的操作部分结果。操作部包括执行算术逻辑运算并输出运算结果的运算部，基于控制信号保持与运算结果相关的状态的标志寄存器，以及用于连续保持与运算结果相关的预定状态的缓冲器。操作单元通过选择性地读取保持在标志寄存器和缓冲器中的状态来执行算术逻辑运算。

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