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71. 发明申请

US20120156889A1 METHODS FOR FORMING HIGH-K CRYSTALLINE FILMS AND RELATED DEVICES 有权
标题翻译：用于形成高K晶体薄膜和相关器件的方法
公开(公告)号：US20120156889A1
公开(公告)日：2012-06-21
申请号：US13334618
申请日：2011-12-22
申请人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra Malhotra , Xiangxin Rui
发明人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra Malhotra , Xiangxin Rui
IPC分类号： H01L21/316
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L28/56 , H01L28/60
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
摘要翻译：本公开提供了制造半导体堆叠和相关联的器件（诸如电容器或DRAM单元）的方法。在这种器件中，高K氧化锆基层可以与基于氮化钛的相对廉价的金属电极一起用作主要电介质。为了防止在器件形成期间电极的损坏，可以使用薄的阻挡层，在使用高温工艺和（高浓度或剂量）的臭氧试剂之前密封电极（即，产生高K氧化锆基层）。在一些实施例中，阻挡层也可以是基于氧化锆的，例如掺杂或未掺杂的无定形氧化锆的薄层。以这种方式制造器件有助于基于氧化锆和氮化钛形成具有大于40的介电常数的器件，并且通常有助于产生更便宜的，越来越致密的DRAM电池和其它半导体结构。

72. 发明申请

US20110151136A1 METHODS FOR DEPOSITING HIGH-K DIELECTRICS 有权
标题翻译：沉积高K电介质的方法
公开(公告)号：US20110151136A1
公开(公告)日：2011-06-23
申请号：US13039819
申请日：2011-03-03
申请人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
发明人： Xiangxin Rui , Sunil Shanker , Sandra Malhotra , Imran Hashim , Edward Haywood
IPC分类号： B05D3/06 , B05D3/02 , B05D5/12
CPC分类号： H01L21/3141 , C23C16/02 , C23C16/405 , H01L21/02186 , H01L21/02271 , H01L21/02315 , H01L21/31604 , H01L28/91
摘要： Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
摘要翻译：描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

73. 发明申请

US20100001269A1 Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
标题翻译：在半导体基板上筛选多个样品的组合处理方法
公开(公告)号：US20100001269A1
公开(公告)日：2010-01-07
申请号：US12167118
申请日：2008-07-02
申请人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
发明人： Gaurav Verma , Kurt Weiner , Prashant Phatak , Imran Hashim , Sandra Malhotra , Tony Chiang
IPC分类号： C23C16/00 , H01L21/66 , H01L23/58
CPC分类号： G01R31/2831 , G01R31/2834 , H01L22/34
摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
摘要翻译：在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

74. 发明申请

US20070222066A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20070222066A1
公开(公告)日：2007-09-27
申请号：US11308433
申请日：2006-03-24
申请人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
发明人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

75. 发明申请

US20050199502A1 Method for electroplating on resistive substrates 审中-公开
标题翻译：电阻基板电镀方法
公开(公告)号：US20050199502A1
公开(公告)日：2005-09-15
申请号：US11123117
申请日：2005-05-06
申请人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
发明人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
IPC分类号： C25D5/18 , C25D7/12 , C25D5/02
CPC分类号： C25D5/18 , C25D7/12 , Y10S428/926 , Y10T428/12493 , Y10T428/12528 , Y10T428/12771 , Y10T428/12778 , Y10T428/12903
摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
摘要翻译：导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。

76. 发明申请

US20050110142A1 Diffusion barriers formed by low temperature deposition 审中-公开
标题翻译：通过低温沉积形成的扩散壁垒
公开(公告)号：US20050110142A1
公开(公告)日：2005-05-26
申请号：US10722934
申请日：2003-11-26
申请人： Michael Lane , Christian Lavoie , Sandra Malhotra , Fenton McFeely , John Yurkas
发明人： Michael Lane , Christian Lavoie , Sandra Malhotra , Fenton McFeely , John Yurkas
IPC分类号： H01L21/285 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/28556 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A solid state device includes a first material and a second material. A barrier layer is formed between the first material and the second material to prevent diffusion between the first material and the second material. The barrier layer includes a metal form of at least one of Ru and Re. The barrier layer is preferably formed using a low temperature deposition process, where the substrate is less than 400 degrees C.
摘要翻译：固体装置包括第一材料和第二材料。在第一材料和第二材料之间形成阻挡层以防止第一材料和第二材料之间的扩散。阻挡层包括Ru和Re中的至少一种的金属形式。阻挡层优选使用低温沉积工艺形成，其中衬底小于400℃。

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