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71. 发明申请

WO2004107421A1 FORMATION OF JUNCTIONS AND SILICIDES WITH REDUCED THERMAL BUDGET 审中-公开
标题翻译：形成具有减少热量预算的结和硅
公开(公告)号：WO2004107421A1
公开(公告)日：2004-12-09
申请号：PCT/IB2004/050753
申请日：2004-05-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , PAWLAK, Bartlomiej, J.
发明人： PAWLAK, Bartlomiej, J.
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/26513 , H01L21/28044
摘要： Method of formation of a metal-silicide layer (12, 13, 14, 18, 19) an a semiconductor substrate (1), the semiconductor substrate (1) including at least a dopant region (5); the dopant region (5) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region (5); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer (12, 13, 18, 19) an the dopant region (5), and the method including, as a third step carried out after the ferst and the second step, a low-temperature annealing process wherein simultaneously the dopant region (5) is activated and the metal-silicide layer (12, 13, 14, 18, 19) is formed.
摘要翻译：形成半导体衬底（1）的金属硅化物层（12,13,14,18,19）的形成方法，所述半导体衬底（1）至少包括掺杂剂区域（5）; 所述掺杂剂区域（5）包括超浅结区域; 该方法包括用于形成掺杂剂区域（5）的至少一种杂质注入工艺（IB掺杂剂）作为第一步骤; 该方法包括用于形成掺杂剂区域（5）的金属硅化物层（12,13,18,19）的至少一种金属注入工艺（IB金属）作为第二步骤，并且该方法包括作为第三步骤在第一阶段和第二阶段之后执行低温退火工艺，其中同时激活掺杂剂区域（5）并形成金属硅化物层（12,13,14,18,19）。

72. 发明申请

WO2004070834A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SUCH A METHOD 审中-公开
标题翻译：制造这种方法的半导体器件和半导体器件的制造方法
公开(公告)号：WO2004070834A1
公开(公告)日：2004-08-19
申请号：PCT/IB2004/050030
申请日：2004-01-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , LANDER, Robert , KNOTTER, Dirk, M.
发明人： LANDER, Robert , KNOTTER, Dirk, M.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , Y10S438/976
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (2) comprising a first (N-MOS)FET (3) with a first channel region (3A) and a first gate electrode (3B) which includes a first conductor and which is separated from the channel region by a dielectric layer (4), and comprising a second (P-MOS)FET (5) with a second channel region (5A) and a second gate electrode (5B) which includes a second conductor that is different from the first conductor and which is separated from the channel region (5A) by a dielectric layer (4), wherein to form the gate electrodes (3B, 5B) a first conductor layer (33) is deposited on the semiconductor body (2) provided with the dielectric layer (4), which layer (33) is subsequently removed outside the first channel region (3A) after which a second conductor layer (55) is deposited on the semiconductor body (2), and wherein before the first conductor layer (33) is deposited, an intermediate layer (6) is deposited on the dielectric layer (4). According to the invention, a material for the intermediate layer (6) is chosen which is selectively etchable with respect to the dielectric layer (4), and before the deposition of the first conductor layer (33) the intermediate layer (6) is removed at the location of the firs channel region (3A), and after the deposition of the first conductor layer (33) and the removal thereof outside the first channel region (3A) and before the deposition of the second conductor layer (55), the intermediate layer (6) is removed at the location of the second channel region (5A). Thus, FETs are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer (8) is deposited on the intermediate layer (6) which is selectively etchable with respect thereto.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（1）和半导体本体（2），所述半导体本体（2）包括具有第一沟道区（3A）的第一（N-MOS）FET（3）栅电极（3B），其包括第一导体，并且通过介电层（4）与沟道区分离，并且包括具有第二沟道区（5A）的第二（P-MOS）FET（5）和第二沟道区栅电极（5B），其包括与所述第一导体不同的第二导体，并且通过电介质层（4）与所述沟道区（5A）分离，其中，形成所述栅极（3B，5B）的第一导体层（33）沉积在设置有电介质层（4）的半导体本体（2）上，该层（33）随后在第一沟道区域（3A）之外被移除，之后第二导体层（55）沉积在半导体本体（2），并且其中在第一导体层（33）沉积之前， ayer（6）沉积在介电层（4）上。根据本发明，选择用于中间层（6）的材料，其相对于电介质层（4）可选择性地蚀刻，并且在沉积第一导体层（33）之前，中间层（6）被去除在第一通道区域（3A）的位置处，并且在第一导体层（33）沉积之后并且将其除去在第一沟道区域（3A）之外并且在第二导体层（55）的沉积之前，在第二通道区域（5A）的位置处去除中间层（6）。因此，以简单的方式获得FET并且不损坏其栅极电介质。优选地，在中间层（6）上沉积另外的中间层（8），中间层（6）可相对于其可选择性地蚀刻。

73. 发明申请

WO2003046756A3 SCHEMA, SYNTACTIC ANALYSIS METHOD AND METHOD OF GENERATING A BIT STREAM BASED ON A SCHEMA 审中-公开
公开(公告)号：WO2003046756A3
公开(公告)日：2003-06-05
申请号：PCT/BE2002/000178
申请日：2002-11-26
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , KONINKLIJKE PHILIPS ELECTRONICS N.V. , OSORIO, Roberto
发明人： OSORIO, Roberto
IPC分类号： H04N7/24
摘要： A method and apparatus for transforming a description of an encoded bit stream is described. The encoded bit stream comprises data packets and the description is written in a markup language such as BSDL. A group of one or more data packets is described in said description by an element, said element having at least one attribute containing a transformation tag. The description is scanned to check for a transformation tag in accordance with a predetermined condition and an adapted description is generated. The transformation of multimedia files is described to provide for content scalability. The adaptation approach works as follows: instead of directly adapting the bit stream, the description of the bit stream is modified, by use of so-called style sheets. Therefore, from the modified description a binary form file can be generated.

74. 发明申请

WO2003046756A2 A METHOD FOR SYNTACTICALLY ANALYSING A BIT STREAM USING A SCHEMA AND A METHOD OF GENERATING A BIT STREAM BASED THEREON 审中-公开
标题翻译：用于使用示意图来综合分析位流的方法及其生成基于位流的方法
公开(公告)号：WO2003046756A2
公开(公告)日：2003-06-05
申请号：PCT/BE2002/000178
申请日：2002-11-26
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , KONINKLIJKE PHILIPS ELECTRONICS N.V. , OSORIO, Roberto
发明人： OSORIO, Roberto
IPC分类号： G06F17/30
CPC分类号： G06F17/2258 , G06F17/2247 , G06F17/227 , G06F17/271 , H04N19/124 , H04N19/154 , H04N19/162 , H04N19/17 , H04N19/187 , H04N19/61 , H04N19/63 , H04N19/65 , H04N19/70 , H04N19/89
摘要： A method and apparatus for transforming a description of an encoded bit stream is described. The encoded bit stream comprises data packets and the description is written in a markup language such as BSDL. A group of one or more data packets is described in said description by an element, said element having at least one attribute containing a transformation tag. The description is scanned to check for a transformation tag in accordance with a predetermined condition and an adapted description is generated. The transformation of multimedia files is described to provide for content scalability. The adaptation approach works as follows: instead of directly adapting the bit stream, the description of the bit stream is modified, by use of so-called style sheets. Therefore, from the modified description a binary form file can be generated.
摘要翻译：描述用于变换编码比特流的描述的方法和装置。编码比特流包括数据分组，并且描述以诸如BSDL的标记语言编写。在所述描述中通过元素描述一组一个或多个数据分组，所述元素具有至少一个包含变换标签的属性。扫描描述以根据预定条件检查变换标签，并且生成适应的描述。描述多媒体文件的转换以提供内容可扩展性。适应方法的工作原理如下：代替直接调整比特流，通过使用所谓的样式表来修改比特流的描述。因此，从修改后的描述可以生成二进制形式的文件。

75. 发明申请

WO2010072246A1 METHOD FOR RESIST DEVELOPMENT IN NARROW HIGH ASPECT RATIO VIAS 审中-公开
标题翻译：方法用于低速高比例VIAS中的抗性发展
公开(公告)号：WO2010072246A1
公开(公告)日：2010-07-01
申请号：PCT/EP2008/068143
申请日：2008-12-22
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , PHAM, Phuong Nga
发明人： PHAM, Phuong Nga
IPC分类号： H01L21/027 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/76898
摘要： A method for developing a resist layer inside high aspect ratio vias in a substrate comprising the steps of: (a) applying masked illumination to make certain areas of the resist layer inside the vias soluble and other areas of the resist layer insoluble in a liquid developing solution; (b) applying the liquid developing solution to the resist layer during a predetermined development time for developing the resist layer; (c) removing the liquid developing solution from the resist layer after the predetermined development time. Step b) comprises applying ultrasonic agitation for a predetermined duration to ensure full development of the soluble areas within the predetermined development time.
摘要翻译：一种用于在衬底中形成高纵横比通孔内的抗蚀剂层的方法，包括以下步骤：（a）施加掩蔽照明，以使抗蚀剂层的某些区域位于可溶解的抗蚀剂层的可渗透区域中，并且抗蚀剂层的其它区域不溶于液体显影解; （b）在用于显影抗蚀剂层的预定显影时间期间将液体显影溶液施加到抗蚀剂层; （c）在预定的显影时间之后从抗蚀剂层除去液体显影液。步骤b）包括在预定持续时间内施加超声波搅拌以确保在预定开发时间内完全展开可溶性区域。

76. 发明申请

WO2010038216A1 PHASE CHANGE MEMORY CELLS AND FABRICATION THEREOF 审中-公开
标题翻译：相变记忆细胞及其制备
公开(公告)号：WO2010038216A1
公开(公告)日：2010-04-08
申请号：PCT/IB2009/054313
申请日：2009-10-02
申请人： NXP B.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , KOCHUPURACKAL, Jinesh, B. P. , WOLTERS, Robertus, A. M. , ZANDT, Michael, A. A.
发明人： KOCHUPURACKAL, Jinesh, B. P. , WOLTERS, Robertus, A. M. , ZANDT, Michael, A. A.
IPC分类号： H01L45/00
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/12 , H01L45/1675
摘要： A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ≥ 5nm.
摘要翻译：相变存储器单元，例如线电池（2）及其制造，所述电池包括：两个电极（6,8）; 相变记忆材料（10）和电介质阻挡层（12）。电介质势垒（12）被布置成提供电子隧穿，例如 Fowler-Nordheim隧道，到相变记忆材料（10）。还可以提供由相变记忆材料制成的触点（15）。电介质势垒（12）基本上是均匀的基本均匀的厚度，例如 = 5nm。

77. 发明申请

WO2010020897A1 GRINGO HETEROJUNCTION BIPOLAR TRANSISTOR WITH A METAL EXTRINSIC BASE REGION 审中-公开
标题翻译：具有金属极地基区域的GRINGO异相双极晶体管
公开(公告)号：WO2010020897A1
公开(公告)日：2010-02-25
申请号：PCT/IB2009/053401
申请日：2009-08-05
申请人： NXP B.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , BOCCARDI, Guillaume , KRAMER, Mark, C., J., C., M. , DONKERS, Johannes, J., T., M. , CHOI, Li, Jen , DECOUTERE, Stefaan , SIBAJA-HERNANDEZ, Arturo , VAN HUYLENBROECK, Stefaan , VENEGAS, Rafael
发明人： BOCCARDI, Guillaume , KRAMER, Mark, C., J., C., M. , DONKERS, Johannes, J., T., M. , CHOI, Li, Jen , DECOUTERE, Stefaan , SIBAJA-HERNANDEZ, Arturo , VAN HUYLENBROECK, Stefaan , VENEGAS, Rafael
IPC分类号： H01L21/331 , H01L21/8249
CPC分类号： H01L29/1004 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66287
摘要： The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.
摘要翻译：本发明涉及一种包括衬底（1）的半导体器件（30），包括集电极区（3），基极区（4）和发射极区域（15））的双极晶体管的半导体本体（25），其中所述集电极区域（3）的至少一部分被第一隔离区域（2,8）包围，所述半导体本体（25）还包括以与所述基极区域接触的方式布置的非本征基极区域（35） 4）。以这种方式，获得了具有减小的寄生分量影响的快速半导体器件。

78. 发明申请

WO2010003928A2 METHOD FOR DOPING SEMICONDUCTOR STRUCTURES AND THE SEMICONDUCTOR DEVICE THEREOF 审中-公开
标题翻译：半导体结构的掺杂方法及其半导体器件
公开(公告)号：WO2010003928A2
公开(公告)日：2010-01-14
申请号：PCT/EP2009/058529
申请日：2009-07-06
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) , LOO, Roger , LEYS, Frederik , CAYMAX, Matty
发明人： LOO, Roger , LEYS, Frederik , CAYMAX, Matty
IPC分类号： H01L21/225 , H01L29/10
CPC分类号： H01L29/66795 , H01L21/2254 , H01L21/2256 , H01L29/1054 , H01L29/66803 , H01L29/7842
摘要： A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.
摘要翻译：一种用于将物质引入应变半导体层的方法，包括：提供包括第一区域和第二区域的衬底，所述第一区域包括暴露的应变半导体层，将所述衬底装载到反应室中，然后形成共形第一物质，至少在暴露的应变半导体层上，然后进行热处理，由此使第一种类的至少一部分从第一种类层扩散到应变半导体层中，并且至少部分地激活在应变半导体层中扩散的第一类物质。

79. 发明申请

WO2009122347A2 MULTIPLE BIT PHASE CHANGE MEMORY CELL 审中-公开
标题翻译：多位相变存储器单元
公开(公告)号：WO2009122347A2
公开(公告)日：2009-10-08
申请号：PCT/IB2009/051327
申请日：2009-03-30
申请人： NXP B.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , GOUX, Ludovic, R., A. , GILLE, Thomas , LISONI, Judit, G. , WOUTERS, Dirk, J., C., C., M. , MARDEN, David, I.
发明人： GOUX, Ludovic, R., A. , GILLE, Thomas , LISONI, Judit, G. , WOUTERS, Dirk, J., C., C., M. , MARDEN, David, I.
IPC分类号： H01L45/00
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1683
摘要： A phase change memory cell has more than one memory region (14,18) each being a narrowed region of phase change memory material (2) extending between first and second electrodes (4,6). Each of the plurality of memory regions (14, 18) can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.
摘要翻译：相变存储器单元具有多于一个存储区域（14,18），每个存储器区域是在第一和第二电极（4,6）之间延伸的相变存储器材料（2）的变窄区域。可以通过施加电流和/或电压的合适的编程条件，将多个存储区域（14,18）中的每一个编程为处于低电阻状态或高电阻状态。高电阻状态的电阻和将高电阻状态转换为低电阻状态的编程条件在多个存储区域中的每一个中是不同的。

80. 发明申请

WO2009122345A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：WO2009122345A1
公开(公告)日：2009-10-08
申请号：PCT/IB2009/051324
申请日：2009-03-30
申请人： NXP B.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , SINGANAMALLA, Raghunath , HOOKER, Jacob, C. , VAN DAL, Marcus, J., H.
发明人： SINGANAMALLA, Raghunath , HOOKER, Jacob, C. , VAN DAL, Marcus, J., H.
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/28 , H01L21/336
CPC分类号： H01L21/82345 , H01L21/265 , H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g. less than 10 nm, over the dielectric layer (130), depositing a second metal layer (150) having a second thickness over the first metal layer (140), the second thickness being larger than the first thickness, introducing a dopant (152, 154) into the second metal layer (150), exposing the device to an increased temperature to migrate at least some of the dopant (152, 154) from the second metal layer (150) beyond the interface between the first metal layer (140) and the second metal layer (150); and patterning the stack into a number of gate electrodes (170). This way a gate electrode is formed having an dopant profile in the vicinity of the dielectric layer (130) such that the work function of the gate electrode is optimized, without the gate dielectric suffering from degradation by dopant penetration.
摘要翻译：公开了一种制造具有合适功函材料的栅极的半导体器件的方法。该方法包括提供包括多个有源区（110,120）和覆盖有源区（110,120）的介电层（130）的衬底（100），以及形成层叠层（140,150,160）在介电层上。堆叠层的形成包括沉积具有第一厚度的第一金属层（140）在所述电介质层（130）上方小于10nm，在所述第一金属层（140）上沉积具有第二厚度的第二金属层（150），所述第二厚度大于所述第一厚度， 154）插入到第二金属层（150）中，使该器件暴露于升高的温度以将来自第二金属层（150）的至少一些掺杂剂（152,154）从第一金属层（140）和第二金属层（150）; 以及将所述堆叠图案化成多个栅电极（170）。这样，在电介质层（130）附近形成具有掺杂剂分布的栅电极，使得优化栅电极的功函数，而不会使掺杂剂渗透的栅电介质劣化。

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