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71. 发明授权

US07508986B2 Document recognition device, document recognition method and program, and storage medium 有权
标题翻译：文件识别装置，文件识别方法和程序以及存储介质
公开(公告)号：US07508986B2
公开(公告)日：2009-03-24
申请号：US10997537
申请日：2004-11-23
申请人： Hiroaki Ikeda , Keiko Nakanishi , Taeko Gotoh
发明人： Hiroaki Ikeda , Keiko Nakanishi , Taeko Gotoh
IPC分类号： G06K9/00 , G06K9/34 , G06K9/62 , G06K9/68
CPC分类号： G06K9/00449
摘要： In document recognition processing for accurately recognition a document image at high speed, a shape feature is extracted from a component included in an input document image, and the degree of similarity of shape between the document image and the registered document is calculated based on the extracted shape feature. When it is determined that the component of the document image has color information, the color information is extracted from the document image, thus calculating the degree of similarity of color information from the document image. The degree of similarity of shape is corrected based on the degree of similarity of color information, thus determining that the registered document is similar to the document image.
摘要翻译：在用于以高速精确地识别文档图像的文档识别处理中，从包括在输入文档图像中的分量提取形状特征，并且基于提取的文档图像来计算文档图像和注册文档之间的形状相似度形状特征。当确定文档图像的分量具有颜色信息时，从文档图像中提取颜色信息，从而从文档图像计算颜色信息的相似度。基于颜色信息的相似度来校正形状的相似度，从而确定登记的文档类似于文档图像。

72. 发明申请

US20070285179A1 SIGNAL DISTRIBUTION ARCHITECTURE AND SEMICONDUCTOR DEVICE 失效
标题翻译：信号分配架构和半导体器件
公开(公告)号：US20070285179A1
公开(公告)日：2007-12-13
申请号：US11744694
申请日：2007-05-04
申请人： Hiroaki Ikeda , Mamoru Sasaki , Atsushi Iwata , Mitsuru Shiozaki , Atsushi Mori
发明人： Hiroaki Ikeda , Mamoru Sasaki , Atsushi Iwata , Mitsuru Shiozaki , Atsushi Mori
IPC分类号： H03B9/14
CPC分类号： H03B5/1841 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.
摘要翻译：提供了一种能够减小传输线上的驻波的幅度差并从任何位置提供信号的网格式的高速时钟信号分配网络。用于发送时钟信号的网络使得差分信号传输线的端部经由电感器连接，通过电感器中的相移来消除低幅度段，并且产生基本均匀的相位和幅度的驻波，其中连接到网格点的线数对于整个网格点是相同的。

73. 发明申请

US20070252273A1 SEMICONDUCTOR DEVICE HAVING A SMALLER ELECTROSTATIC CAPACITANCE ELECTRODE 有权
标题翻译：具有小型静电电容电极的半导体器件
公开(公告)号：US20070252273A1
公开(公告)日：2007-11-01
申请号：US11741532
申请日：2007-04-27
申请人： Masakazu Ishino , Hiroaki Ikeda
发明人： Masakazu Ishino , Hiroaki Ikeda
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05011 , H01L2224/05022 , H01L2224/05023 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05548 , H01L2224/05568 , H01L2224/05644 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10253 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have a thickness less than 0.6 mm. The thick island insulating films reduces an electrostatic capacitance of the pad electrodes to reduce the propagation delay of a signal passing through the pad electrodes.
摘要翻译：半导体封装包括覆盖形成在硅衬底上的内部电路的均匀的薄绝缘膜。在各个焊盘电极之下形成多个厚岛绝缘膜，其将内部电路连接到外部电路。硅衬底从底部抛光到厚度小于0.6mm。厚岛绝缘膜减小了焊盘电极的静电电容，以减少通过焊盘电极的信号的传播延迟。

74. 发明申请

US20070228456A1 LAMINATED MEMORY HAVING AUTONOMICALLY AND SEQUENTIALLY ACTIVATING OPERATION 失效
标题翻译：具有自动和顺序激活操作的层压记忆体
公开(公告)号：US20070228456A1
公开(公告)日：2007-10-04
申请号：US11690032
申请日：2007-03-22
申请人： Hiroaki Ikeda , Junji Yamada
发明人： Hiroaki Ikeda , Junji Yamada
IPC分类号： H01L29/792
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L27/0688 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： In a laminated memory, each of memory core layers includes a delay circuit having a period of delay time corresponding to a period of operation time of an internal memory circuit portion thereof. A memory core layer, which is input with a simultaneous operation signal, operates in response to the input operation signal. The delay circuit includes an autonomically and sequentially activating function for sending an operation signal to a next stage after the period of delay time passes.
摘要翻译：在层叠存储器中，每个存储核心层包括具有对应于其内部存储器电路部分的操作时间周期的延迟时间的延迟电路。输入同时操作信号的存储核心层响应于输入操作信号而工作。延迟电路包括在延迟时间过去之后将操作信号发送到下一级的自动和顺序启动功能。

75. 发明授权

US07241533B1 Electrode for rechargeable lithium battery and rechargeable lithium battery 失效
标题翻译：可充电锂电池和可充电锂电池电极
公开(公告)号：US07241533B1
公开(公告)日：2007-07-10
申请号：US10111075
申请日：2000-10-20
申请人： Hiroaki Ikeda , Masahisa Fujimoto , Shin Fujitani , Kenji Asaoka , Shigeki Matsuta , Yoichi Domoto , Ryuji Ohshita , Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroshi Kurokawa , Yoshio Kato , Hiroshi Nakajima , Toshikazu Yoshida
发明人： Hiroaki Ikeda , Masahisa Fujimoto , Shin Fujitani , Kenji Asaoka , Shigeki Matsuta , Yoichi Domoto , Ryuji Ohshita , Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroshi Kurokawa , Yoshio Kato , Hiroshi Nakajima , Toshikazu Yoshida
IPC分类号： H01M4/70 , H01M4/36
CPC分类号： H01M4/661 , H01M2/0207 , H01M4/04 , H01M4/131 , H01M4/134 , H01M4/1395 , H01M4/366 , H01M4/38 , H01M4/386 , H01M4/40 , H01M4/405 , H01M4/485 , H01M4/525 , H01M4/58 , H01M4/667 , H01M4/70 , H01M6/40 , H01M10/052 , H01M10/0587 , H01M10/44 , H01M2010/4292
摘要： An electrode for a rechargeable lithium battery characterized in that thin films of active material capable of lithium storage and release, i.e., microcrystalline or amorphous silicone thin films are deposited on opposite faces of a plate-form current collector.
摘要翻译：一种用于可再充电锂电池的电极，其特征在于，在板形集电器的相对面上沉积能够储存和释放锂的活性材料的薄膜，即微晶或非晶硅薄膜。

76. 发明授权

US07162086B2 Character recognition apparatus and method 有权
标题翻译：字符识别装置及方法
公开(公告)号：US07162086B2
公开(公告)日：2007-01-09
申请号：US10615304
申请日：2003-07-09
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G06K9/18
CPC分类号： G06K9/6821
摘要： A character recognition apparatus which performs character recognition with increased accuracy on a document image including plural languages. A re-recognition range is set based on the result of recognition using a first recognition unit, and character recognition by a second recognition unit is performed within the set range. In the re-recognition range, if a similarity of the result of re-recognition is higher than that by the first recognition unit, the result of recognition by the first recognition unit is replaced with the result of recognition by the second recognition unit.
摘要翻译：一种字符识别装置，其对包括多种语言的文档图像进行精度更高的字符识别。基于使用第一识别单元的识别结果设置重新识别范围，并且在设定范围内执行第二识别单元的字符识别。在重新识别范围中，如果重新识别的结果的相似度高于第一识别单元的相似度，则第一识别单元的识别结果被第二识别单元的识别结果所取代。

77. 发明申请

US20070001281A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070001281A1
公开(公告)日：2007-01-04
申请号：US11476145
申请日：2006-06-28
申请人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
发明人： Masakazu Ishino , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
摘要翻译：半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。该器件具有插入器芯片。连接到芯片的第一内部电极形成在插入器芯片的第一表面上。连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。只要需要，接口芯片可以安装在插入器芯片的第二表面上。因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。因此，核心芯片不需要以裸芯片的形式大量存放。

78. 发明授权

US07123497B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07123497B2
公开(公告)日：2006-10-17
申请号：US10828189
申请日：2004-04-21
申请人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/06
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
摘要翻译：在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与系统数据信号，已经清楚的是对系统数据信号的传送速率有限制，并且不能期望加速。构成存储器模块的多个DRAM中的电流消耗大，这也是妨碍加速的因素。获得了一种存储器模块，其中多个DRAM芯片堆叠在IO芯片上，并且其中每个DRAM芯片通过通孔连接到IO芯片，并且其包括用于相互转换系统数据信号和内部数据信号由每个DRAM芯片由IO芯片组成。在这种结构中，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

79. 发明申请

US20050286334A1 Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：US20050286334A1
公开(公告)日：2005-12-29
申请号：US11151213
申请日：2005-06-14
申请人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： G11C5/04 , G11C5/06 , G11C8/00 , H01L25/065
CPC分类号： G11C5/04 , G11C5/063 , H01L25/0657 , H01L2224/16145 , H01L2225/06527 , H01L2225/06555 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.
摘要翻译：具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片在堆叠的方向。

80. 发明授权

US06887511B1 Method for preparing electrode material for lithium battery 失效
标题翻译：锂电池用电极材料的制备方法
公开(公告)号：US06887511B1
公开(公告)日：2005-05-03
申请号：US10111078
申请日：2000-10-20
申请人： Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroaki Ikeda , Masahisa Fujimoto , Shin Fujitani , Yoichi Domoto
发明人： Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroaki Ikeda , Masahisa Fujimoto , Shin Fujitani , Yoichi Domoto
IPC分类号： C23C14/02 , C23C14/14 , C23C16/02 , C23C16/24 , H01M4/1391 , H01M4/1393 , H01M4/1395 , H01M4/1397 , H01M4/36 , H01M4/38 , H01M4/64 , H01M4/70 , H01M6/00 , H01M10/05
CPC分类号： H01M4/0428 , H01M4/04 , H01M4/0404 , H01M4/0419 , H01M4/0421 , H01M4/0426 , H01M4/366 , H01M4/64 , H01M4/70 , H01M10/052 , H01M2004/021 , Y10T29/49108 , Y10T29/49115
摘要： A method for preparing an electrode material for a lithium battery, characterized in that a noncrystalline silicon thin film that serves as an active material is deposited on a substrate.
摘要翻译：一种锂电池用电极材料的制造方法，其特征在于，在基板上沉积作为活性物质的非晶硅薄膜。

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