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71. 发明专利

JP4439803B2 Manufacturing data analysis method and a program to run it on your computer 有权
公开(公告)号：JP4439803B2
公开(公告)日：2010-03-24
申请号：JP2002350968
申请日：2002-12-03
申请人：富士通マイクロエレクトロニクス株式会社
发明人：英大白井
IPC分类号： H01L21/02 , G06Q50/00 , G06Q50/04
CPC分类号： Y02P90/30

72. 发明专利

JP4439023B2 Semiconductor device and a display device 有权
公开(公告)号：JP4439023B2
公开(公告)日：2010-03-24
申请号：JP33169598
申请日：1998-11-20
申请人：富士通マイクロエレクトロニクス株式会社
发明人：政利國分 , 真也鵜戸
IPC分类号： H01L21/3205 , H01L21/82 , G02F1/136 , G02F1/1368 , H01L23/52 , H01L29/786 , H03K17/693 , H03M1/76

73. 发明专利

JP4437881B2 Micro controller having a debug support unit 有权
公开(公告)号：JP4437881B2
公开(公告)日：2010-03-24
申请号：JP2001189750
申请日：2001-06-22
申请人：富士通マイクロエレクトロニクス株式会社
发明人：達岡林 , 耕太郎田川
IPC分类号： G06F11/22 , G06F11/28 , G06F11/36 , G06F15/78
CPC分类号： G06F11/3636 , G06F11/3648 , G06F11/3656

74. 发明专利

JP4437710B2 Semiconductor memory 有权
公开(公告)号：JP4437710B2
公开(公告)日：2010-03-24
申请号：JP2004191947
申请日：2004-06-29
申请人：富士通マイクロエレクトロニクス株式会社
发明人：広之小林 , 達哉神田
IPC分类号： G11C11/407 , G11C8/08 , G11C11/403 , G11C11/406 , G11C11/408
CPC分类号： G11C11/4085 , G11C8/08 , G11C2207/2227 , G11C2211/4067

75. 发明专利

JP2010062864A Transmitter and receiver 审中-公开
标题翻译：发射机和接收机
公开(公告)号：JP2010062864A
公开(公告)日：2010-03-18
申请号：JP2008226359
申请日：2008-09-03
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： ASAHINA SHUGO
IPC分类号： H04L27/34
摘要： PROBLEM TO BE SOLVED: To provide a transmitter which is superior in power efficiency and can comparatively easily process encoding and decoding of a signal point at high speed. SOLUTION: The transmitter includes: a first encoder which when a plurality of hexagons having sizes multiplied by serial natural number are drawn at the same center on an I/Q plane and a ratio of the plural hexagons is m in size, encodes data to a signal point with a power of 2 wherein 6×m signal points are arranged at apexes and on sides of the respective hexagons; and a transmitting section for transmitting transmission data based on the encoded signal points. In the transmitter, the first encoder is provided with an area calculator (901) which divides the signal points into a plurality of areas and calculates an area to which the signal points of the data among the plurality of areas belong, a range calculator (902) which calculates a hexagon to which the signal points of the data among the plurality of hexagons belong, and a position calculator (903) which calculates a position to which the signal points of the data on the hexagons belong. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供功率效率优异并且可以相对容易地以高速度处理信号点的编码和解码的发射机。解决方案：发射机包括：第一编码器，当在I / Q平面上的同一中心绘制具有乘以串联自然数的尺寸的多个六边形并且多个六边形的比例大小为m时，进行编码数据到功率为2的信号点，其中6×m个信号点布置在相应六边形的顶点和侧面; 以及发送部，用于基于编码信号点发送发送数据。在发射机中，第一编码器设置有区域计算器（901），其将信号点划分成多个区域，并且计算出属于多个区域中的数据的信号点的区域，范围计算器（902 ），其计算出所述多个六边形中的数据的信号点所属的六边形和计算六边形上的数据的信号点所在位置的位置计算器（903）。版权所有（C）2010，JPO＆INPIT

76. 发明专利

JP2010061514A Method and device for designing semiconductor integrated circuit 有权
标题翻译：用于设计半导体集成电路的方法和装置
公开(公告)号：JP2010061514A
公开(公告)日：2010-03-18
申请号：JP2008228183
申请日：2008-09-05
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： FUKUDA TATSUYA , NAGASAKA MITSUAKI
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To provide a method and device for designing a semiconductor integrated circuit, which reduce a circuit modification cost by reducing the number of revision layers in modifying a circuit while considering a wiring pattern after modifying the circuit. SOLUTION: The design method is implemented by the design device for designing the semiconductor integrated circuit. The design device is achieved by the design method of carrying out an extraction procedure for extracting connection information between cells connected to a plurality of wiring layers, from a net list; a reading procedure for reading physical data including cell layout data and wiring shape data showing the shape of wiring between the cells; and a determining procedure for determining the layout positions of additional cells based on the physical data and the connection information of the lowermost wiring layer among a plurality of wiring layers. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于设计半导体集成电路的方法和装置，其通过在修改电路之后考虑布线图案的同时减少修改电路中的修订层的数量来降低电路修改成本。
解决方案：设计方法由设计半导体集成电路的设计器件实现。该设计装置是通过从网络列表中执行从连接到多个布线层的单元之间提取连接信息的提取过程的设计方法来实现的; 用于读取包括单元布局数据的物理数据和示出单元之间布线形状的布线形状数据的读取过程; 以及基于多个布线层中的最下布线层的物理数据和连接信息来确定附加单元的布局位置的确定步骤。版权所有（C）2010，JPO＆INPIT

77. 发明专利

JP2010060307A Method for controlling fluid supply device 审中-公开
标题翻译：控制流体供应装置的方法
公开(公告)号：JP2010060307A
公开(公告)日：2010-03-18
申请号：JP2008223356
申请日：2008-09-01
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： MIZUTANI TERUHIRO
IPC分类号： G01N1/16 , B01J4/00 , G01N27/62 , H01L21/02
摘要： PROBLEM TO BE SOLVED: To stably supply a fluid of constant quality from a fluid supply device.
SOLUTION: The fluid is enclosed in the flow channel of the fluid supply device for a definite time and the change amount per unit time of the impurity component in the flow channel is calculated from the amounts of the impurity component in the fluid before and after the enclosure of the fluid (steps S1-S5). Then, the change amount is compared with a preset allowable change amount to determine the quality of the fluid enclosed in the flow channel or the cleanness of the flow channel (steps S6 and S7). After constant quality is confirmed, the supply of the fluid from the fluid supply device is started.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：从流体供应装置稳定地供应恒定质量的流体。解决方案：流体被封闭在流体供应装置的流动通道中一定时间，并且流动通道中的杂质组分的每单位时间的变化量根据流体中的杂质组分的量计算并在流体封闭之后（步骤S1-S5）。然后，将变化量与预设的允许变化量进行比较，以确定流路中包围的流体的质量或流路的清洁度（步骤S6和S7）。在确定恒定质量之后，开始从流体供应装置供应流体。版权所有（C）2010，JPO＆INPIT

78. 发明专利

JP4434539B2 Processor and the boot method 有权
公开(公告)号：JP4434539B2
公开(公告)日：2010-03-17
申请号：JP2001394157
申请日：2001-12-26
申请人：富士通マイクロエレクトロニクス株式会社 , 富士通周辺機株式会社
发明人：健夫佐々木 , 隆伸柏木 , 章二谷口 , 功一黒岩
IPC分类号： G06F11/10 , G06F1/32 , G06F9/445
CPC分类号： G06F9/4401
摘要： A processor and method of booting the processor and provided in which dispensable circuit operation is eliminated to reduce power consumption. A first expected check-sum value relating to instructions and table data and a second expected check-sum value relating only to instructions are held in a boot ROM (5). When power is turned on, if a power-on determination circuit (2) determines that the power has been turned on for a system, a read selection circuit (3) loads instructions and the table data into an instruction storage memory (7) and a table data storage memory (8) and a check-sum performing circuit (4) performs check-sum using the first expected check-sum value. In the case where the power has been turned on for periodic operation, instructions are loaded into the instruction storage memory (7), check-sum is performed using the second expected check-sum value, and table data that was saved in a backup memory (6) is loaded into the table data storage memory (8). Thus, the time required for loading from the boot ROM (5) for the periodic operation decreases.

79. 发明专利

JP2010056578A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010056578A
公开(公告)日：2010-03-11
申请号：JP2009277893
申请日：2009-12-07
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： IKEMASU SHINICHIRO , OKAWA SHIGEMI
IPC分类号： H01L21/8242 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To facilitate planarization by stabilizing a capacity of a DRAM and reducing the difference in height between a memory cell part and a peripheral circuit part. SOLUTION: A first contact plug is buried in a first insulating film on a memory cell transistor, and second and third insulating films different in etching characteristics are formed, and a contact window piercing the second and third insulating layers is formed, and a cylinder type storage electrode is formed, and the third insulating film is removed with the second insulating film as an etching stopper, and a capacitor insulating film and a conductive film are formed and are patterned to form a counter electrode, and the second insulating film also is removed in accordance with the counter electrode to form a memory cell, and a conductive film and an insulating film are formed on the first insulating film in a peripheral edge area, and a second contact plug is buried in them. An end part of the second insulating film is not brought into contact with the second contact plug. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了通过稳定DRAM的容量并减小存储单元部分和外围电路部分之间的高度差来促进平坦化。解决方案：第一接触插塞埋在存储单元晶体管的第一绝缘膜中，形成不同蚀刻特性的第二和第三绝缘膜，形成穿透第二绝缘层和第三绝缘层的接触窗口，形成圆柱型存储电极，用第二绝缘膜作为蚀刻停止层去除第三绝缘膜，形成电容器绝缘膜和导电膜，并形成对电极，第二绝缘膜还根据对电极去除以形成存储单元，并且在周边区域中的第一绝缘膜上形成导电膜和绝缘膜，并且在其中埋入第二接触插塞。第二绝缘膜的端部不与第二接触插塞接触。版权所有（C）2010，JPO＆INPIT

80. 发明专利

JP2010056306A Cmos solid-state imaging apparatus and production method therefor 有权
标题翻译： CMOS固态成像装置及其生产方法
公开(公告)号：JP2010056306A
公开(公告)日：2010-03-11
申请号：JP2008219951
申请日：2008-08-28
申请人： Fujitsu Microelectronics Ltd , 富士通マイクロエレクトロニクス株式会社
发明人： DAIKU HIROSHI
IPC分类号： H01L27/146 , H04N5/335 , H04N5/361 , H04N5/369 , H04N5/374
摘要： PROBLEM TO BE SOLVED: To solve the problem of the changes in the shading properties from one color component to another, due to the oblique incidence of incident light into a light-receiving region in a CMOS solid-state imaging device.
SOLUTION: The CMOS solid-state imaging device includes a silicon substrate on which a light-receiving region is defined, and a plurality of light-receiving elements which are arrayed in the light-receiving regions and each make up pixels. Each of the light-receiving elements is formed in the silicon substrate and includes a diffusion region which is a component of a photodiode. The depth of the diffusion region measured from the surface of the silicon substrate is a minimum at the pixel, at the center of the light-receiving region and is increased higher at the pixel in the surrounding region than at the pixel of the center section.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了解决由于在CMOS固态成像装置中入射到光接收区域的入射光的倾斜入射，从一个颜色分量到另一个颜色分量的阴影特性的变化的问题。解决方案：CMOS固态成像器件包括其上限定有光接收区域的硅衬底和排列在光接收区域中的每个构成像素的多个光接收元件。每个光接收元件形成在硅衬底中，并且包括作为光电二极管的成分的扩散区域。从硅衬底的表面测量的扩散区域的深度在光接收区域的中心处的像素处最小，并且在周围区域的像素处比在中心部分的像素处增加得更高。版权所有（C）2010，JPO＆INPIT

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