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61. 发明公开

EP0403215A3 Flip-flop circuit 失效
标题翻译：触发器电路
公开(公告)号：EP0403215A3
公开(公告)日：1993-07-21
申请号：EP90306371.7
申请日：1990-06-12
申请人： NEC CORPORATION
发明人： Tago, Shusei
IPC分类号： H03K3/286 , H03K3/289 , H03K3/2885 , H03K3/12
CPC分类号： H03K3/289 , H03K3/2885
摘要： A Flip-Flop circuit, of a current-pass switching type logical circuit, of the invention comprises a pair of data holding transistors (Q₁₁,Q₁₂), the emitters thereof being tied together at a first junction point (22) and being led to a constant-current source (18); and a set signal input transistor (Q₁₈) and a reset signal input transistor (Q₁₉), the emitters thereof being tied together at a second junction point (21) and being led to the constant-current source. There is provided a single level-shifting resistor (20) between the first junction point (22) and the second junction point (21) for preventing interference or concurrence between the high level of a set signal or a reset signal and the high level of the internal data held by the data holding transistors (Q₁₁,Q₁₂). The circuit is suitable to be fabricated in a semiconductor integrated circuit device of high packing density. The working range of power supply voltages for the circuit is wide because the level shift voltage developed across the level-shifting resistor is not influenced by the variation of the power supply voltage.
摘要翻译：本发明的电流通道切换型逻辑电路的触发器电路包括一对数据保持晶体管（Q 11，Q 12），它们的发射极在第一连接点（22）处连接在一起并被引导到一个恒流源（18）; 和一个置位信号输入晶体管（Q 18）和一个复位信号输入晶体管（Q 18），它们的发射极在第二个连接点（21）连接在一起并被引导到恒流源。在第一接合点（22）和第二接合点（21）之间提供了单个电平移动电阻器（20），用于防止设置信号的高电平或复位信号与高电平之间的干扰或并发由数据保持晶体管（Q 11，Q 12）保持的内部数据。该电路适合于制造在高封装密度的半导体集成电路器件中。电路的电源电压的工作范围很宽，因为在电平移动电阻上产生的电平移动电压不受电源电压变化的影响。

62. 发明公开

EP0386541A3 Non-current hogging dual phase splitter TTL circuit 失效
标题翻译：非电流相位双相分路器TTL电路
公开(公告)号：EP0386541A3
公开(公告)日：1991-01-09
申请号：EP90103497.5
申请日：1990-02-23
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Jansson, Lars
IPC分类号： H03K19/088 , H03K19/003 , H03K3/286
CPC分类号： H03K3/288 , H03K19/00307 , H03K19/00353 , H03K19/088
摘要： Dual phase splitter transistor elements (Q5, Q51), an output phase splitter transistor element (Q5) and a secondary phase splitter transistor element (Q51), are coupled in current mirror configuration in a TTL output buffer circuit (10). The output phase splitter transistor element (Q5) is coupled to the pullup (Q1, Q3) and pulldown (Q2) transistor elements for controlling the respective conducting states of the pullup (Q1, Q3) and pulldown (Q2) transistor elements. The collector of the secondary phase splitter transistor element (Q51) is coupled in a supplemental circuit which can have a variable load without direct connection to the pullup transistor element (Q1, Q3) and output (Vout). A low impedance current sourcing active transistor element (Q40) is coupled in emitter follower configuration at the collector node of the secondary phase splitter transistor element (Q51) for supplying mirroring current through the emitter of the secondary phase splitter transistor element (Q51) to reduce current hogging at the dual phase splitter transistor elements (Q5, Q51). The current sourcing transistor element (Q40) is coupled in parallel with the supplemental circuit thereby providing a variable current which varies inversely with the collector current supplied by the supplemental circuit. The invention is applied in a JK flip flop circuit at the output buffer circuits (46) with the collector of the secondary phase splitter transistor element (Q51) coupled to the cross feedback circuit. The cross feedback transistor element (Q8) in the cross feedback circuit is therefore isolated from the pullup transistor element (Q1, Q3) and output avoiding feedback transistor breakdown when the output is at high potential. The current sourcing transistor element (Q40) prevents current hogging between the dual phase splitter transistor elements (Q5, Q51).

63. 发明公开

EP0244054A2 Laser diode driver 失效
标题翻译：激光Dioden-二极管驱动器。
公开(公告)号：EP0244054A2
公开(公告)日：1987-11-04
申请号：EP87300796.7
申请日：1987-01-29
申请人： TEKTRONIX, INC.
发明人： Agoston, Agoston
IPC分类号： H01S3/096 , H03K3/33 , H03K17/60 , H03K3/286
CPC分类号： H03K3/33 , H01S5/042 , H03K3/286 , H03K17/601
摘要： A reverse current transmitted through an initially forward biased step-recovery diode causes the step-recovery diode to switch from the forward biased state to a reverse biased state, thereby developing an abruptly rising reverse bias voltage across the step-recovery diode. The abruptly rising reverse bias voltage is applied across a series combination of a capacitor and a laser diode, connected in parallel with the step-recovery diode to force a short, abrupt forward current pulse through the laser diode, thereby causing the laser diode to emit a short optical pulse.
摘要翻译：通过初始正向偏置的阶跃恢复二极管传输的反向电流使得步进恢复二极管从正向偏置状态转换到反向偏置状态，从而在逐步恢复二极管两端产生突然上升的反向偏置电压。突然升高的反向偏置电压施加在电容器和激光二极管的串联组合之间，与阶跃恢复二极管并联连接，以迫使通过激光二极管的短暂的，突然的正向电流脉冲，从而使激光二极管发射一个短的光脉冲。

64. 发明公开

EP0205972A1 Digital circuit with improved input noise margin. 失效
标题翻译： Digitale Schaltung mitEingangsstörabstand。
公开(公告)号：EP0205972A1
公开(公告)日：1986-12-30
申请号：EP86107257
申请日：1986-05-28
申请人： IBM
发明人： FAVATA ALFRED FILADELFIO , GAUDENZI GENE JOSEPH
IPC分类号： H03K3/286 , H03K5/00 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00353
摘要： A digital circuit with a logical input stage (4) and an output stage (7, 8) comprises an intermediate stage (5) which operates to temporarily increase the current through the input stage (4) upon a transition from one logical level to the other. The intermediate stage (5) includes a current source (40) which is controlled by the output potential of the input stage (4) via a feedback arrangement (43) from a circuit (50) in the intermediate stage (5) controlling the output stage (7, 8).
摘要翻译：具有逻辑输入级（4）和输出级（7,8）的数字电路包括中间级（5），该中间级（5）用于在从一个逻辑电平转换到其他。中间级（5）包括电流源（40），该电流源通过来自中间级（5）中的电路（50）的反馈装置（43）由输入级（4）的输出电位控制输出阶段（7,8）。

65. 发明公开

EP0111055A3 LATCH CIRCUIT WITH DIFFERENTIAL CASCODE CURRENT SWITCH LOGIC 失效
标题翻译：具有差分电流开关逻辑的锁存电路
公开(公告)号：EP0111055A3
公开(公告)日：1986-12-30
申请号：EP83108571
申请日：1983-08-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： LEININGER, JOEL CALVIN
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/086 , H03K3/288
CPC分类号： H03K19/086 , H03K3/2885

66. 发明公开

EP0097164A4 LATCHABLE FAST SETTLING DIGITAL-TO-ANALOG CONVERTER BIT SWITCH. 失效
标题翻译： LOCKING快速调整数模转换器BITSCH时代。
公开(公告)号：EP0097164A4
公开(公告)日：1986-05-16
申请号：EP82903114
申请日：1982-09-21
申请人： MOTOROLA INC
发明人： SMITH GREGORY J
IPC分类号： H03K3/286 , H03K3/2885 , H03K17/60 , H03M1/00 , H03K13/02
CPC分类号： H03K3/2885 , H03M1/74

67. 发明公开

EP0052669A1 Mehrfach adressierbarer hochintegrierter Halbleiterspeicher 有权
标题翻译：多个寻址高度集成的半导体存储器。
公开(公告)号：EP0052669A1
公开(公告)日：1982-06-02
申请号：EP80107368.5
申请日：1980-11-26
申请人： IBM DEUTSCHLAND GMBH , International Business Machines Corporation
发明人： Berger, Horst, Dr. , Wiedmann, Siegfried, Dr.
IPC分类号： G06F13/00 , G11C8/00 , G11C11/40 , H03K3/286
CPC分类号： G11C8/16
摘要： Es wird ein mehrfach adressierbarer hochintegrierter Halbleiterspeicher vorgeschlagen, dessen Speicherplätze in Kreuzungspunkten von Wortleitungen und Bitleitungen liegen und über mehrere unabhängige Adreßsysteme zum parallelen Lesen und/oder Schreiben ansteuerbar sind, wobei die Speicherplätze aus n Speicherelementen (FF) bestehen. Ein Speicherplatz besteht z.B. mindestens aus zwei Flip-Flops (FF), die über Koppelglieder (KLO, KL1) mit zugeordneten, voneinander verschiedenen Bitleitungen (R (A), R (B), WR (C)) und mit getrennten Wortleitungen (WLA, WLB) verbunden sind. Jede Zelle weist mindestens drei unabhängig selektierbare bzw. adressierbare Zugänge ((A), (B), (C)) auf, wodurch folgende Operationen jeweils möglich sind: Parallel Lesen Wort A, Lesen Wort B, Schreiben Wort C und jede beliebige Zweierkombination oder einzelne der drei Operationen. Die Anzahl der Lesezugänge über weitere zusätzliche Adreßsysteme ist erweiterbar und die Anwendungen von Triple-, Quadrupel- usw. Speicherzellen anstelle eines Zellenpaares (CP) möglich.
摘要翻译：提出了一种多个寻址高度集成的半导体存储器，其存储器位置是在字线和位线的交叉点，并且可以通过用于并行读取和/或写入数个独立的地址系统，其特征在于，N个存储元件（FF）的存储场所存在来控制。的空间是例如联接构件（出的kl0，KL1）具有相关联的，相互不同的位线（R（A），R（B），WR（C）），并与单独的字线（WLA，WLB）连接的至少两个触发器（FF），是。每个单元具有至少三个独立地进行selektivierbare或寻址访问（（A），（B），（C）），由此以下操作在每种情况下是可能的：并行读出字A，读出字B，写入字C和两种的任意组合或三个操作的一个。进一步附加的地址系统的读出的访问的数量可以扩展，和三重等Quadrupel-存储器单元的应用程序，而不是一个小区对（CP）是可能的。

68. 发明授权

EP2887395B1 Nonvolatile latch circuit and logic circuit, and semiconductor device using the same 有权
公开(公告)号：EP2887395B1
公开(公告)日：2019-05-08
申请号：EP15154322.0
申请日：2010-10-29
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kato, Kiyoshi , Koyama, Jun
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/8242 , H01L27/00 , H01L27/088 , H01L27/10 , H01L27/108 , H01L29/786 , H03K3/037 , H03K3/356 , H03K19/00 , H03K19/0948 , H03K19/096 , G11C14/00 , G11C7/04 , G11C16/04 , H01L21/02 , H01L21/28 , H01L29/66 , H01L27/12 , H03K3/286

69. 发明授权

EP2502272B1 NONVOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：不挥发锁定电路和逻辑电路半导体器件
公开(公告)号：EP2502272B1
公开(公告)日：2015-04-15
申请号：EP10831470.9
申请日：2010-10-29
申请人： Semiconductor Energy Laboratory Co. Ltd.
发明人： KATO, Kiyoshi , KOYOMA, Jun
IPC分类号： H01L27/105 , H01L21/8234 , H01L21/8242 , H01L27/00 , H01L27/088 , H01L27/10 , H01L27/108 , H01L29/786 , H03K3/037 , H03K3/356 , H03K19/00 , H03K19/0948 , H03K19/096 , G11C14/00 , G11C7/04 , G11C16/04 , H01L21/02 , H01L21/28 , H01L29/66 , H01L27/12 , H03K3/286
CPC分类号： H03K3/356104 , G11C7/04 , G11C14/0063 , G11C16/045 , G11C2211/4016 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/28202 , H01L21/28211 , H01L27/105 , H01L27/1203 , H01L27/1225 , H01L29/6659 , H03K3/0375 , H03K3/286 , H03K3/356 , H03K3/356121 , H03K3/356173

70. 发明公开

EP1490969A2 LOW-POWER CMOS FLIP-FLOP 审中-公开
标题翻译： CMOS FLIP具有低功耗FLOPS
公开(公告)号：EP1490969A2
公开(公告)日：2004-12-29
申请号：EP03716979.4
申请日：2003-04-04
申请人： The Regents of The University of Michigan
发明人： ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
IPC分类号： H03K3/037 , H03K3/12 , H03K3/286
CPC分类号： H03K3/356121
摘要： A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

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