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61. 发明申请

US20040246019A1 Inspection device and inspection method for active matrix panel, and manufacturing method for active matrix organic light emitting diode panel 失效
标题翻译：有源矩阵面板的检查装置和检查方法，以及有源矩阵有机发光二极管面板的制造方法
公开(公告)号：US20040246019A1
公开(公告)日：2004-12-09
申请号：US10848318
申请日：2004-05-18
申请人： International Business Machines Corporation
发明人： Daiju Nakano , Yoshitami Sakaguchi
IPC分类号： G01R031/00
CPC分类号： G09G3/006 , G09G3/3225 , G09G2300/0842 , G09G2330/10
摘要： An inspection method includes an array process of forming a TFT array on a substrate to fabricate an active matrix panel, an inspection process of carrying out a performance test on the fabricated active matrix panel, and a cell process of mounting an OLED on the active matrix panel after the inspection process. In the inspection process, variation in parasitic capacitance through a pixel electrode is measured when driving TFTs constituting the active matrix fabricated in the array process are turned on and when the driving TFTs are turned off, and open/short defects in the driving TFTs are thereby inspected.
摘要翻译：检查方法包括在基板上形成TFT阵列以制造有源矩阵面板的阵列处理，对制造的有源矩阵面板执行性能测试的检查过程以及将OLED安装在有源矩阵上的单元工艺检查过程后面板。在检查过程中，当构成阵列处理中制造的有源矩阵的TFT被驱动并且当驱动TFT被截止时，测量驱动TFT中的开/短缺陷时，通过像素电极的寄生电容的变化，检查。

62. 发明申请

US20040246018A1 TFT array inspection device 失效
标题翻译： TFT阵列检测装置
公开(公告)号：US20040246018A1
公开(公告)日：2004-12-09
申请号：US10834874
申请日：2004-04-30
申请人： SHIMADZU CORPORATION
发明人： Chikuya Takada
IPC分类号： G01R031/00
CPC分类号： G09G3/006
摘要： A TFT array inspection device inspects a TFT array substrate having thin film transistors arranged in a matrix pattern. The TFT array inspection device includes a probe frame to be electrically connected to the TFT array substrate. The probe frame includes probe pins contacting array inspection electrodes to be connected to a driving electrode terminal provided in a TFT array on the TFT array substrate through wires. The probe pins are positioned at common locations relative to a layout of the TFT array substrate. Since the probe pins are located at common positions, it is possible to use a single common probe frame for the TFT array substrate with a different layout without providing or changing a prove frame corresponding to a different layout of the TFT array substrate.
摘要翻译： TFT阵列检查装置检查具有以矩阵图案排列的薄膜晶体管的TFT阵列基板。 TFT阵列检查装置包括与TFT阵列基板电连接的探针架。探针框架包括探针，其接触阵列检查电极，以通过导线连接到设置在TFT阵列基板上的TFT阵列中的驱动电极端子。探针位于相对于TFT阵列基板的布局的公共位置。由于探针位于公共位置，所以可以使用具有不同布局的TFT阵列基板的单个公共探针框架，而不提供或改变对应于TFT阵列基板的不同布局的证明框架。

63. 发明申请

US20040230395A1 Universally accessible fully programmable memory built-in self-test (MBIST) system and method 有权
标题翻译：通用的完全可编程存储器内置的自检（MBIST）系统和方法
公开(公告)号：US20040230395A1
公开(公告)日：2004-11-18
申请号：US10776762
申请日：2004-02-11
发明人： Luis Antonio Basto
IPC分类号： G01R031/00 , G01R031/14
CPC分类号： G11C29/56004 , G11C29/10 , G11C29/16 , G11C29/20 , G11C29/56 , G11C2029/0405
摘要： A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under test, a sequencer circuit configured to deliver test data to selected addresses of the memory under test and reading out that test data, a comparator circuit configured to compare the test data read out of the memory under test to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable pattern register for providing a pattern of test data to the memory under test. The system includes an external pattern programming device configured to supply the pattern of test data to the user programmable data pattern register.
摘要翻译：一种普遍可访问的完全可编程存储器内置自检（MBIST）系统，其包括MBIST控制器，该MBIST控制器具有地址发生器，该地址发生器被配置为产生被测存储器的地址;定序器电路，被配置为将测试数据传送到被测存储器的所选地址并且读出该测试数据;比较器电路，被配置为将从所测试的存储器读出的测试数据与传递到被测存储器的测试数据进行比较，以识别存储器故障;以及外部可访问的用户可编程模式寄存器，测试数据的模式到被测内存。该系统包括被配置为将测试数据的模式提供给用户可编程数据模式寄存器的外部模式编程设备。

64. 发明申请

US20040222813A1 Method and apparatus for testing liquid crystal display 有权
标题翻译：液晶显示器测试方法及装置
公开(公告)号：US20040222813A1
公开(公告)日：2004-11-11
申请号：US10665576
申请日：2003-09-22
发明人： Jong Dam Kim , Hyun Kyu Lee , Yong Jin Cho , See Hwa Jeong
IPC分类号： G01R031/00
CPC分类号： G09G3/006
摘要： A method and apparatus are provided for inspecting an electrical defectiveness of a liquid crystal display substrate. The method includes shorting ESD protection devices with a conductive shorting bar to form a current path on each of signal wirings of the substrate, supplying a current to the signal wirings, and determining a defectiveness of the signal wirings depending on the current flowing on the signal wirings.
摘要翻译：提供了一种用于检查液晶显示基板的电气缺陷性的方法和装置。该方法包括用导电短路棒短路ESD保护装置，以在基板的每个信号布线上形成电流路径，向信号布线提供电流，以及根据在信号上流动的电流来确定信号布线的缺陷布线。

65. 发明申请

US20040209172A1 Defect correction method for a photomask 审中-公开
标题翻译：光掩模的缺陷校正方法
公开(公告)号：US20040209172A1
公开(公告)日：2004-10-21
申请号：US10809593
申请日：2004-03-25
发明人： Osamu Takaoka , Kazuo Aita , Fumio Aramaki
IPC分类号： G03F009/00 , G06F017/50 , G01L021/30 , C23F003/00 , C23F001/00 , B44C001/22 , G01R031/00
CPC分类号： G03F1/74 , C03C17/28 , G03F1/30
摘要： In order to enable the correction of clear defects, opaque defects, and Levenson mask glass projection defects using one species of gas, by changing gas pressure and probe current and scanning conditions of the ion beam 2, the diacetone acrylamide is capable of forming a light-blocking film 17 correcting clear defects on a glass substrate 16 and a chrome pattern 15, is capable of removing chrome and glass at a high etching rate, and is capable of eliminating opaque defect regions 18 and eliminating glass projection defect regions 19. It is therefore possible to carry out correction by changing gas supplying conditions and ion beam irradiation conditions according to whether the correction is clear defect correction, opaque defect correction, or Levenson mask glass projection defect correction.
摘要翻译：为了能够通过改变气体压力和探针电流以及离子束2的扫描条件来校正清晰缺陷，不透明缺陷和利文森掩模玻璃投影缺陷，双丙酮丙烯酰胺能够形成光在玻璃基板16和铬图案15上校正清晰的缺陷的阻挡膜17能够以高蚀刻速度去除铬和玻璃，并且能够消除不透明缺陷区域18并消除玻璃投影缺陷区域19.它是因此可以根据校正是否清晰的缺陷校正，不透明缺陷校正或者列文森掩模玻璃投影缺陷校正来改变供气条件和离子束照射条件来进行校正。

66. 发明申请

US20040207521A1 Trainline controller electronics 有权
公开(公告)号：US20040207521A1
公开(公告)日：2004-10-21
申请号：US10845089
申请日：2004-05-14
申请人： New York Air Brake Corporation
发明人： Anthony W. Lumbis , Dale R. Stevens , John N. Versic
IPC分类号： G01R031/00 , G08B029/00
CPC分类号： B61L15/0036 , B61L15/0054 , B61L15/0081 , G08C19/16
摘要： Trainline controller including testing of signal quality on a trainline network by commanding each node to transmitter calibration signal. A signal detector is connected to the trainline at a common junction with a head end termination circuit. A stuck-on transmitter is determined by a transmission current drawn by the transceiver is on for a present amount of time.

67. 发明申请

US20040199843A1 Tiered built-in self-test (BIST) architecture for testing distributed memory modules 有权
标题翻译：分层内置自检（BIST）架构，用于测试分布式内存模块
公开(公告)号：US20040199843A1
公开(公告)日：2004-10-07
申请号：US10630516
申请日：2003-07-29
发明人： David W. Hansquine , Roberto F. Averbuj
IPC分类号： G06F019/00 , G01R027/28 , G01R031/00 , G01R031/14 , G01R031/28
CPC分类号： G11C29/16
摘要： A distributed, hierarchical built-in self-test (BIST) architecture for testing the operation of one or more memory modules is described. As described, the architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces coupled to memory modules. The BIST controller stores a set of commands that generically define an algorithm for testing the memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers receive the commands and generate sequences of memory operations in accordance with the timing requirements of the various memory modules. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands.
摘要翻译：描述了用于测试一个或多个存储器模块的操作的分布式分层内置自检（BIST）架构。如上所述，架构包括三层抽象层：集中式BIST控制器，一组排序器以及一组耦合到存储器模块的存储器接口。 BIST控制器存储一组命令，通常定义用于测试存储器模块的算法，而不考虑存储器模块的物理特性或时序要求。定序器根据各种存储器模块的时序要求接收命令并产生存储器操作序列。存储器接口根据存储器模块的物理特性将存储器操作应用于存储器模块，例如通过基于存储器模块的行列排列来转换地址和数据信号，以实现由命令描述的位模式。

68. 发明申请

US20040153925A1 Integrated memory and method for testing an integrated memory 失效
标题翻译：用于测试集成内存的集成内存和方法
公开(公告)号：US20040153925A1
公开(公告)日：2004-08-05
申请号：US10726990
申请日：2003-12-03
发明人： Mario Di Ronza , Yannick Martelloni , Volker Schober
IPC分类号： G06F019/00 , G01R027/28 , G01R031/00 , G01R031/14 , G01R031/28
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/72 , G11C2029/1208
摘要： An integrated memory and method for testing an integrated memory is provided herein. In order to test an integrated memory having a main data memory (SP) with a plurality of data memory units, a data memory unit is addressed and input test data for testing the addressed data memory unit are applied to the main data memory (SP). The output test data are read out from the main data memory (SP) and compared with expected desired output test data in a self-test unit (STE). Deviations detected during the comparison are buffer-stored in a redundancy analysis memory (RAS). These information items buffer-stored in the redundancy analysis memory (RAS) are read out and transferred to a computing unit (RE). In the computing unit (RE), the defect positions in the output test data are identified, and a repair strategy is determined by means of redundant rows and/or redundant columns and/or redundant words provided. The redundant words required for the repair strategy are written to the redundancy analysis memory (RAS) and activated.
摘要翻译：本文提供了用于测试集成存储器的集成存储器和方法。为了测试具有多个数据存储单元的主数据存储器（SP）的集成存储器，寻址数据存储单元，并将用于测试寻址数据存储单元的输入测试数据应用于主数据存储器（SP）。输出测试数据从主数据存储器（SP）中读出，并与自检单元（STE）中的期望输出测试数据进行比较。在比较期间检测到的偏差被缓冲存储在冗余分析存储器（RAS）中。缓冲存储在冗余分析存储器（RAS）中的这些信息项被读出并传送到计算单元（RE）。在计算单元（RE）中，识别输出测试数据中的缺陷位置，并且通过冗余行和/或冗余列和/或提供的冗余字确定修复策略。将修复策略所需的冗余字写入冗余分析存储器（RAS）并激活。

69. 发明申请

US20040124844A1 Process and device for testing electric motors, in particular fan motors, for functionality 失效
标题翻译：用于测试电动机，特别是风扇电机的功能的过程和装置
公开(公告)号：US20040124844A1
公开(公告)日：2004-07-01
申请号：US10736469
申请日：2003-12-15
发明人： Andreas Gruhle , Horst Kibbel
IPC分类号： G01R031/00 , G01R031/08
CPC分类号： G01R31/343
摘要： The invention concerns a device for and a process for testing electric motors, in particular fan motors, for functionality, wherein electromagnetic alternating fields produced by an electric motor are received by an antenna, wherein the received signals are analyzed for signal components in the frequency range of the rotation value of electric motors or their harmonics via an analysis unit, and wherein upon determination of functionality the results are indicated by an indicator unit.
摘要翻译：本发明涉及用于测试用于功能的电动机，特别是风扇电动机的装置和方法，其中由电动机产生的电磁交变磁场由天线接收，其中对频率范围内的信号分量进行分析通过分析单元的电动机的旋转值或其谐波，并且其中在确定功能时，结果由指示器单元指示。

70. 发明申请

US20040111231A1 INTEGRATED CIRCUITS HAVING POST-SILICON ADJUSTMENT CONTROL 有权
标题翻译：具有后置硅调整控制的集成电路
公开(公告)号：US20040111231A1
公开(公告)日：2004-06-10
申请号：US10707450
申请日：2003-12-15
发明人： Yoshiyuki Ando
IPC分类号： G06F019/00 , G01R031/00 , G01R027/28
CPC分类号： G01R31/31707 , G01R31/319
摘要： An integrated circuit system has a reference data table for holding information that is used to control at least one circuit block in the system and also has a power supply circuit, a body bias control circuit, a clock delivery circuit, a temperature monitor circuit, and/or a configuration control circuit. The performance of the system is improved by obtaining system performance data by testing the system at different supply voltages, different body-bias voltages, different clock speeds, and/or different temperatures. Values based on the data are entered into the reference data table. The power supply circuit, the body bias control circuit, the clock delivery circuit, and/or the temperature monitor circuit data is adjusted using the entered values.
摘要翻译：集成电路系统具有用于保持用于控制系统中的至少一个电路块的信息的参考数据表，并且还具有电源电路，体偏置控制电路，时钟传递电路，温度监视电路和 /或配置控制电路。通过在不同的电源电压，不同的体偏置电压，不同的时钟速度和/或不同的温度下测试系统来获得系统性能数据，来提高系统的性能。基于数据的值被输入到参考数据表中。使用输入的值来调整电源电路，主体偏置控制电路，时钟传送电路和/或温度监视器电路数据。

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