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61. 发明申请

US20130273868A1 ACTIVE ANTENNA ARRAY FOR A MOBILE COMMUNICATIONS NETWORK WITH A PLURALITY OF GAIN SWITCHES AND A METHOD FOR ADJUSTING A SIGNAL LEVEL OF INDIVIDUAL RADIO SIGNALS 有权
标题翻译：用于具有多重增益切换的移动通信网络的主动天线阵列和用于调整个体无线电信号的信号电平的方法
公开(公告)号：US20130273868A1
公开(公告)日：2013-10-17
申请号：US13915082
申请日：2013-06-11
申请人： Peter Kenington
发明人： Peter Kenington
IPC分类号： H04B1/18
CPC分类号： H04B1/18 , H01Q3/26 , H03M1/123 , H03M1/185 , H03M3/466 , H03M3/49
摘要： An active antenna array for a mobile communications network and a method for receiving radio signals is disclosed. The active antenna array has a plurality of antenna elements for relaying radio signals, a plurality of first amplifiers for amplifying a plurality of individual receive signals a plurality of first analogue-to-digital converters and a plurality of first gain switches located between one of the plurality of first analogue-to-digital converters and the plurality of first amplifiers. A digital signal processor is connected to outputs of the plurality of first analogue-to-digital converters and has a common gain switch control line connected to at least two of the plurality of first switches for controlling the gain of the first gain switches.
摘要翻译：公开了一种用于移动通信网络的有源天线阵列和用于接收无线电信号的方法。有源天线阵列具有用于中继无线电信号的多个天线元件，用于放大多个单独的接收信号的多个第一放大器，多个第一模拟 - 数字转换器和多个第一增益开关，其位于多个第一模数转换器和多个第一放大器。数字信号处理器连接到多个第一模数转换器的输出，并且具有连接到多个第一开关中的至少两个的公共增益开关控制线，用于控制第一增益开关的增益。

62. 发明申请

US20090212759A1 TRANSFORMER-ISOLATED ANALOG-TO-DIGITAL CONVERTER (ADC) FEEDBACK APPARATUS AND METHOD 有权
标题翻译：变压器分离的模拟数字转换器（ADC）反馈装置和方法
公开(公告)号：US20090212759A1
公开(公告)日：2009-08-27
申请号：US12037932
申请日：2008-02-26
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： G01R19/00 , H03M1/12 , H03M3/00
CPC分类号： H03M3/41 , G01R31/2844 , H03K17/0822 , H03K17/691 , H03M3/466
摘要： A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC for receiving an analog input signal and a transformer having a first winding that receives a modulated output of the analog-to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator is coupled to the second winding of the transformer and demodulates the isolated output to generate a digital representation of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter. The circuit further includes an isolation circuit for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.
摘要翻译：变压器隔离的模数转换器（ADC）反馈装置和方法降低了具有变压器隔离感测电路的大功率/高压系统中的电路复杂性。反馈装置是包括用于接收模拟输入信号的ADC和具有接收模拟 - 数字转换器的调制输出的第一绕组的变压器的电路。变压器的第二个绕组提供了ADC的隔离数据输出。解调器耦合到变压器的第二绕组，并解调隔离输出以产生模拟输入信号的数字表示。 ADC可以是Δ-Σ转换器，并且解调器可以是相应的抽取滤波器。电路还包括用于在变压器的第二绕组处引入时钟信号和/或电源波形的隔离电路，使得ADC电路被提供有隔离时钟和/或隔离电源。

63. 发明授权

US07479911B2 Multiple input multiple output analog-to-digital converter 失效
标题翻译：多输入多输出模数转换器
公开(公告)号：US07479911B2
公开(公告)日：2009-01-20
申请号：US11895630
申请日：2007-08-24
申请人： Shantanu Chakrabartty
发明人： Shantanu Chakrabartty
IPC分类号： H03M3/00
CPC分类号： H03M3/466
摘要： A method is provided for multi-channel analog-to-digital conversion. The method includes: receiving an input vector which represents a plurality of analog signals; transforming the input vector using a linear transformation matrix; converting the transformed input vector to a digital stream using an array of sigma-delta converter; and adapting the linear transform matrix to maximize de-correlation between the signals represented in the input vector.
摘要翻译：提供了一种用于多通道模数转换的方法。该方法包括：接收表示多个模拟信号的输入向量; 使用线性变换矩阵变换输入向量; 使用Σ-Δ转换器的阵列将变换的输入向量转换为数字流; 并适应线性变换矩阵以最大化在输入向量中表示的信号之间的去相关。

64. 发明授权

US6107947A Parallel sigma delta modulator 失效
标题翻译：并行Σ-Δ调制器
公开(公告)号：US6107947A
公开(公告)日：2000-08-22
申请号：US962871
申请日：1997-11-03
申请人： Colin Lyden
发明人： Colin Lyden
IPC分类号： H03M3/02 , H03M3/00
CPC分类号： H03M3/466 , H03M3/43 , H03M3/45 , H03M3/452 , H03M3/454
摘要： In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel so as to provide a sequence of independent outputs available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.
摘要翻译：在Sigma Delta转换器中，以迭代方式处理一系列输入信号采样，以提供一系列与特定频率范围内的输入信号样本匹配的输出信号和反馈信号。并行执行两个或多个连续的迭代，以便提供并行可用的独立输出序列。并行输出的这种提供有助于总体上提高转换器的运行速度，否则转换器滤波器的最大可用时钟速率受到限制。

65. 发明申请

WO2016202636A1 SYSTEMS AND METHODS FOR REDUCING ARTIFACTS AND IMPROVING PERFORMANCE OF A MULTI-PATH ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：减少人为因素的系统和方法，提高多路数模数转换器的性能
公开(公告)号：WO2016202636A1
公开(公告)日：2016-12-22
申请号：PCT/EP2016/062862
申请日：2016-06-07
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LIMITED
发明人： SATOSKAR, Aniruddha , ALLEN, Daniel , SCHNEIDER, Edmund
IPC分类号： H03M1/18 , H04R3/00
CPC分类号： G10K11/175 , H03M1/002 , H03M1/0631 , H03M1/188 , H03M3/466 , H04H20/10 , H04R3/00
摘要： In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise, increase dynamic range, and mask audio artifacts associated with a change in noise floor. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.
摘要翻译：根据本公开的实施例，处理系统可以包括用于处理模拟信号的多个可选择的处理路径，以便降低噪声，增加动态范围，并且掩盖与本底噪声变化相关联的音频伪影。采用技术来在处理路径之间转换并校准两个路径的操作参数，以便减少或消除由处理路径之间的切换引起的伪像。

66. 发明申请

WO2011090045A1 変換装置审中-公开
标题翻译：转换装置
公开(公告)号：WO2011090045A1
公开(公告)日：2011-07-28
申请号：PCT/JP2011/050813
申请日：2011-01-19
申请人：株式会社 Trigence Semiconductor , 安田彰 , 岡村淳一
发明人：安田　彰 , 岡村　淳一
IPC分类号： H03M3/02
CPC分类号： H03M9/00 , H03M3/466
摘要：本発明の一実施形態として、アナログ入力信号をデジタル信号に変換して出力する変換装置であって、前記変換して出力されるデジタル信号にミスマッチシェーピングを行なった後にデジタル－アナログ変換を行なってフィードバック信号を生成するフィードバック信号生成器と、前記アナログ入力信号より前記フィードバック信号を減算して出力する減算器と、前記減算器の出力する信号を複数のパラレル信号に変換して出力するシリアル－パラレル変換器と、前記シリアル－パラレル変換器の出力する複数のパラレル信号に対する信号処理を行ない複数の信号を出力するベクトルフィルタと、前記ベクトルフィルタの出力する複数の信号を量子化してデジタル信号を出力する量子化器と、前記量子化器が出力するデジタル信号をシリアル信号に変換し出力するパラレル－シリアル変換器とを有する変換装置を提供する。
摘要翻译：所公开的转换装置将模拟输入信号转换为数字信号及其输出，其中转换装置包括用于对已转换和输出的数字信号执行失配整形，然后进行数模转换以产生反馈信号; 减法器，用于从模拟输入信号中减去反馈信号并输出; 串行并行转换器，用于将从减法器输出的信号转换为多个并行信号并输出; 矢量滤波器，用于对由串并转换器输出的多个并行信号执行信号处理并输出多个信号; 量化器，用于量化由矢量滤波器输出的多个信号并输出数字信号; 以及用于将由量化器输出的数字信号转换为串行信号并输出的并行串行转换器。

67. 发明申请

WO2009108603A1 TRANSFORMER-ISOLATED ANALOG-TO-DIGITAL CONVERTER (ADC) FEEDBACK APPARATUS AND METHOD 审中-公开
标题翻译：变换器分离的模拟数字转换器（ADC）反馈装置和方法
公开(公告)号：WO2009108603A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/034868
申请日：2009-02-23
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L.
IPC分类号： H03M1/08
CPC分类号： H03M3/41 , G01R31/2844 , H03K17/0822 , H03K17/691 , H03M3/466
摘要： A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC (41) for receiving an analog input signal (Vin) and a transformer (T3) having a first winding that receives a modulated output of the analog- to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator (31, 32) is coupled to the second winding of the transformer and.demodulates the isolated output to generate a digital representation (ADC out) of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter (32). The circuit further includes an isolation circuit (34, 35) for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.
摘要翻译：变压器隔离的模数转换器（ADC）反馈装置和方法降低了具有变压器隔离感测电路的大功率/高压系统中的电路复杂性。反馈装置是包括用于接收模拟输入信号（Vin）的ADC（41）和具有接收模拟 - 数字转换器的调制输出的第一绕组的变压器（T3）的电路。变压器的第二个绕组提供了ADC的隔离数据输出。解调器（31,32）耦合到变压器的第二绕组，并且对隔离输出进行调制，以产生模拟输入信号的数字表示（ADC输出）。 ADC可以是Δ-Σ转换器，并且解调器可以是相应的抽取滤波器（32）。电路还包括用于在变压器的第二绕组处引入时钟信号和/或电源波形的隔离电路（34,35），使得ADC电路被提供有隔离时钟和/或隔离电源。

68. 发明申请

WO2009042386A1 APPARATUS AND METHOD FOR ENCODING A MULTI CHANNEL AUDIO SIGNAL 审中-公开
标题翻译：用于编码多通道音频信号的装置和方法
公开(公告)号：WO2009042386A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/075703
申请日：2008-09-09
申请人： MOTOROLA, INC. , GIBBS, Jonathan, Alastair
发明人： GIBBS, Jonathan, Alastair
IPC分类号： G10L19/00
CPC分类号： G10L19/12 , G10L19/00 , G10L19/008 , G10L19/032 , G10L19/06 , G10L19/087 , G10L19/24 , G10L25/06 , G10L25/12 , G10L25/18 , G10L25/21 , G10L25/24 , H03M3/466 , H04S2400/01 , H04S2420/03
摘要： An encoding apparatus comprises a frame processor (105) which receives a multi channel audio signal comprising at least a first audio signal from a first microphone (101) and a second audio signal from a second microphone (103). An ITD processor (107) then determines an inter time difference between the first audio signal and the second audio signal and a set of delays (109, 111) generates a compensated multi channel audio signal from the multi channel audio signal by delaying at least one of the first and second audio signals in response to the inter time difference signal. A combiner (113) then generates a mono signal by combining channels of the compensated multi channel audio signal and a mono signal encoder (115) encodes the mono signal. The inter time difference may specifically be determined by an algorithm based on determining cross correlations between the first and second audio signals.
摘要翻译：编码设备包括帧处理器（105），其接收包括来自第一麦克风（101）的至少第一音频信号和来自第二麦克风（103）的第二音频信号的多声道音频信号）。然后，ITD处理器（107）确定第一音频信号和第二音频信号之间的时间间隔差，并且一组延迟（109,111）通过延迟至少一个延迟（109,111）来从多声道音频信号生成补偿的多声道音频信号响应于所述中间时间差信号，控制所述第一音频信号和所述第二音频信号中的一个。组合器（113）然后通过组合补偿的多声道音频信号的声道产生单声道信号，单声道信号编码器（115）编码单声道信号。时间间隔差可具体由基于确定第一和第二音频信号之间的互相关的算法来确定。

69. 发明申请

WO2003098808A1 ANALOG-TO-DIGITAL CONVERTER ARRANGEMENT AND METHOD 审中-公开
标题翻译：模拟数字转换器布置和方法
公开(公告)号：WO2003098808A1
公开(公告)日：2003-11-27
申请号：PCT/EP2003/005266
申请日：2003-05-19
申请人： MOTOROLA INC , CLEMENT, Patrick , KHLAT, Nadim
发明人： CLEMENT, Patrick , KHLAT, Nadim
IPC分类号： H03M3/00
CPC分类号： H03M3/466 , H03M3/41
摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).
摘要翻译：一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法第一或第二平移Σ-Δ模数转换器（21,22）的转换。并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

70. 发明公开

EP3308468A1 SYSTEMS AND METHODS FOR REDUCING ARTIFACTS AND IMPROVING PERFORMANCE OF A MULTI-PATH ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：用于减少伪迹和提高多路模拟 - 数字转换器的性能的系统和方法
公开(公告)号：EP3308468A1
公开(公告)日：2018-04-18
申请号：EP16729230.9
申请日：2016-06-07
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： SATOSKAR, Aniruddha , ALLEN, Daniel , SCHNEIDER, Edmund
IPC分类号： H03M1/18 , H04R3/00
CPC分类号： G10K11/175 , H03M1/002 , H03M1/0631 , H03M1/188 , H03M3/466 , H04H20/10 , H04R3/00
摘要： In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise, increase dynamic range, and mask audio artifacts associated with a change in noise floor. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

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