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    • 65. 发明公开
    • Method and apparatus for error correction
    • 用于纠错的方法和设备
    • EP0176099A3
    • 1987-05-13
    • EP85112206
    • 1985-09-26
    • KABUSHIKI KAISHA TOSHIBA
    • Matsushita, Akira c/o Patent Division
    • H04N07/087
    • H04N7/0357H03M13/43
    • According to one aspect of the present invention, an apparatus for error correction is comprised of a data storing section (30) for storing data to be corrected which includes a data field and an error correction field comprised of a predetermined number of bits, a data readout section (100, 40, 90) for reading out, at a first timing, the data to be corrected from the data storing section (30) into a first line, and, at a second timing, into a second line, an error detection section (50, 60) for fetching the data to be corrected as read out into the first line, and for applying a predetermined operation to the data to be corrected, thereby generating, in synchronism with the second timing, correction data corresponding to error data, a correction section (70) for periodically fetching both the data to be corrected as read out into the second line, and the correction data generated by the error detection section (50, 60), and for subjecting the data to a predetermined correction processing to thereby produce corrected data, and a data write section (100, 130, 80) for storing into the data storing section (30) the corrected data as output from the correction section (70).
    • 根据本发明的一个方面,用于纠错的设备包括:数据存储部分(30),用于存储待校正的数据,该数据包括数据字段和由预定数量的比特组成的纠错字段;数据 读出部分(100,40,90),用于在第一时刻从数据存储部分(30)读出要校正的数据到第一行,并且在第二时刻读入第二行,读出部分 检测部分(50,60),用于在读出到第一行中时读取要被校正的数据,并且用于对要校正的数据施加预定操作,由此与第二定时同步地产生与误差相对应的校正数据 数据;一个校正部分(70),用于周期性地提取被读出到第二行中的待校正数据和由错误检测部分(50,60)产生的校正数据,并且用于对数据进行预定校正 处理 从而产生校正数据;以及数据写入部分(100,130,80),用于将从校正部分(70)输出的校正数据存入数据存储部分(30)。
    • 70. 发明专利
    • Error correcting and decoding system
    • 错误修正和解码系统
    • JPS59133751A
    • 1984-08-01
    • JP657983
    • 1983-01-20
    • Nippon Hoso Kyokai
    • YAMADA TSUKASA
    • H03M13/00H03M13/43H04L1/00H04N7/025H04N7/03H04N7/035
    • H03M13/43
    • PURPOSE:To improve the error correcting capacity without deteriorating the error detecting capacity by performing the correction after shifting the bit position when the error correction is impossible. CONSTITUTION:An information bit 200 is obtained when an information part has 190 bits by contracting the original code by a bit, and the bit 200 is turned into a transmission packet signal 205 through a switch 204. At the same time, the bit 200 produces a parity bit through switches 202 and 203 and via an adder 206. Then the signals equivalent to a packet are delivered in the order of the information bit and the parity bit. While a received signal 300 is equal to an input signal to be corrected and has 273 bits with addition of 0 to the data head. A data register 301 stores the data to be corrected, and a syndrome register 302 consists of a shift register of 82 bits. The adders 303-323 produce input signals to be applied to a majority circuit 341. The output 342 of the circuit 341 and the output of the register 301 are supplied to an adder 343. Then the data 344 is delivered after the output of the register 301 is corrected by the error correcting signal 342.
    • 目的:通过在误差校正不可能的位位置后进行校正,可以提高误差校正能力,同时不损害误差检测能力。 构成:当信息部分通过将原始码缩小比特而具有190比特,并且通过开关204将比特200转换成发送分组信号205时,获得信息比特200.同时,比特200产生 通过开关202和203以及经由加法器206的奇偶校验位。然后,以信息位和奇偶校验位的顺序传送等于分组的信号。 而接收信号300等于要校正的输入信号,并且具有添加到数据头的273位。 数据寄存器301存储要校正的数据,并且校正子寄存器302由82位的移位寄存器组成。 加法器303-323产生要施加到多数电路341的输入信号。电路341的输出342和寄存器301的输出被提供给加法器343.然后在寄存器的输出之后传送数据344 301由纠错信号342校正。