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61. 发明申请

US20120057410A1 Method and Apparatus for the Erase Suspend Operation 有权
标题翻译：擦除挂起操作的方法和装置
公开(公告)号：US20120057410A1
公开(公告)日：2012-03-08
申请号：US12875003
申请日：2010-09-02
申请人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
发明人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/345 , G11C16/3454
摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
摘要翻译：非易失性存储器的各个方面具有改进的擦除暂停过程。偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

62. 发明申请

US20110267886A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110267886A1
公开(公告)日：2011-11-03
申请号：US13179714
申请日：2011-07-11
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

63. 发明授权

US07746707B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07746707B2
公开(公告)日：2010-06-29
申请号：US11929210
申请日：2007-10-30
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

64. 发明授权

US07436712B2 Nonvolatile memory device including circuit formed of thin film transistors 有权
公开(公告)号：US07436712B2
公开(公告)日：2008-10-14
申请号：US11979767
申请日：2007-11-08
申请人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
发明人： Taku Ogura , Tadaaki Yamauchi , Takashi Kubo
IPC分类号： G11C11/34 , G11C5/14 , G11C8/00
CPC分类号： G11C16/344 , G11C7/06 , G11C16/0416 , G11C16/12 , G11C16/345 , G11C16/3477 , G11C2207/005
摘要： A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

65. 发明授权

US07433244B2 Flash memory device and related erase operation 有权
标题翻译：闪存设备和相关擦除操作
公开(公告)号：US07433244B2
公开(公告)日：2008-10-07
申请号：US11501070
申请日：2006-08-09
申请人： Chi-Weon Yoon , Heung-Soo Lim
发明人： Chi-Weon Yoon , Heung-Soo Lim
IPC分类号： G11C16/00
CPC分类号： G11C16/16 , G11C16/3409 , G11C16/345 , G11C16/3477
摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.
摘要翻译：闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程行业组。

66. 发明授权

US07430138B2 Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells 有权
标题翻译：使用改变的字线条件来擦除非易失性存储器以补偿较慢的擦除存储器单元
公开(公告)号：US07430138B2
公开(公告)日：2008-09-30
申请号：US11295755
申请日：2005-12-06
申请人： Masaaki Higashitani
发明人： Masaaki Higashitani
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells by different amounts.
摘要翻译：施加到非易失性存储器系统的存储器单元的电压条件在擦除操作期间被改变，以便等同于被同时擦除的系统的其它存储器单元的选择存储器单元的擦除行为。改变的条件可以补偿NAND串中的电容耦合电压。在对NAND串进行擦除操作并开始施加擦除电压脉冲之后，一个或多个内部存储器单元的字线可以浮置。通过浮动所选择的内部字线，跨越与其耦合的单元的隧道电介质区域产生的峰值擦除电位从其正常水平减小。因此，这些单元的擦除速率减慢到基本上与串的较慢的擦除结束存储单元的擦除速率基本一致。不同的字线可以在不同的时间漂浮，以改变不同存储单元的擦除行为。

67. 发明授权

US07227787B2 Method for erasing an NROM cell 有权
标题翻译：擦除NROM单元的方法
公开(公告)号：US07227787B2
公开(公告)日：2007-06-05
申请号：US11415446
申请日：2006-05-01
申请人： Andrei Mihnea , Chun Chen
发明人： Andrei Mihnea , Chun Chen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/0466 , G11C16/14 , G11C16/3409 , G11C16/344 , G11C16/345 , G11C2216/18
摘要： An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a read operation is performed and column current is detected, a high-efficiency recovery operation is performed. If the read operation is performed and column current is not detected, the erase operation has been successfully completed.
摘要翻译：通过擦除存储块来开始擦除氮化物只读存储器（NROM）存储器块的操作。然后可以执行擦除验证操作以确定擦除的成功。如果执行读取操作并且检测到列电流，则执行高效率恢复操作。如果执行了读取操作，并且未检测到列电流，则擦除操作已成功完成。

68. 发明授权

US07200043B2 Nonvolatile memory using a two-step cell verification process 有权
标题翻译：非易失性存储器使用两步细胞验证过程
公开(公告)号：US07200043B2
公开(公告)日：2007-04-03
申请号：US11141145
申请日：2005-05-31
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/3436 , G11C16/345 , G11C16/3459 , G11C2211/5621
摘要： A nonvolatile memory comprises a plurality of memory cells, a bit line control circuit and a verifying circuit. The bit line control circuit includes a driving circuit and a non-driving circuit. The verifying circuit verifies a first threshold voltage of the memory cell when the driving circuit drives the memory cell. The verifying circuit also verifies a second threshold voltage when the driving circuit does not drive the memory cell.
摘要翻译：非易失性存储器包括多个存储单元，位线控制电路和验证电路。位线控制电路包括驱动电路和非驱动电路。当驱动电路驱动存储单元时，验证电路验证存储单元的第一阈值电压。当驱动电路不驱动存储单元时，验证电路还验证第二阈值电压。

69. 发明申请

US20060221709A1 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells 有权
标题翻译：用于使用单独验证擦除非易失性存储器的系统以及对存储器单元子集的额外擦除
公开(公告)号：US20060221709A1
公开(公告)日：2006-10-05
申请号：US11296028
申请日：2005-12-06
申请人： Gerrit Hemink , Teruhiko Kamei
发明人： Gerrit Hemink , Teruhiko Kamei
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
摘要翻译：一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。第一个子集可以包括更快的擦除单元。验证第一个子集包括从验证中排除第二个子集。在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。当第二个子集被验证为擦除时，该组元素被验证为被擦除。验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。

70. 发明申请

US20060221705A1 Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 有权
公开(公告)号：US20060221705A1
公开(公告)日：2006-10-05
申请号：US11295747
申请日：2005-12-06
申请人： Gerrit Hemink , Teruhiko Kamei
发明人： Gerrit Hemink , Teruhiko Kamei
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

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