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61. 发明授权

US09154389B2 Real-time hierarchical protocol decoding 有权
标题翻译：实时分层协议解码
公开(公告)号：US09154389B2
公开(公告)日：2015-10-06
申请号：US14547040
申请日：2014-11-18
申请人： Total Phase, Inc.
发明人： Kumaran Santhanam , Leonid Vaynberg
IPC分类号： G06F3/00 , G06F11/00 , H04L12/26
CPC分类号： G06F11/327 , G06F5/14 , G06F11/0745 , G06F11/0757 , G06F11/221 , G06F11/3027 , G06F11/3041 , G06F11/3048 , G06F11/3093 , G06F2205/062 , H04L43/045 , H04L43/10
摘要： Real-time USB class level decoding is disclosed. In some embodiments, a first packet associated with a USB class level operation associated with a target USB device that is being monitored is received. A second packet generated by a USB hardware analyzer configured to observe USB traffic associated with the target USB device is received. It is determined based at least in part on a time associated with one or both of the first packet and the second packet that the class level operation has timed out.
摘要翻译：披露实时USB级别解码。在一些实施例中，接收与正在监视的目标USB设备相关联的USB等级操作相关联的第一分组。接收由USB硬件分析器生成的第二个数据包，用于观察与目标USB设备相关联的USB流量。至少部分地基于与第一分组和第二分组中的一个或两个相关联的时间来确定类级别操作已经超时。

62. 发明授权

US08738347B2 Method for extracting IBIS simulation model 有权
标题翻译：提取IBIS仿真模型的方法
公开(公告)号：US08738347B2
公开(公告)日：2014-05-27
申请号：US13354109
申请日：2012-01-19
申请人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
发明人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
IPC分类号： G06F17/50 , G06F3/06 , G06F5/06 , G06F5/16 , G06F7/78 , G06F9/54 , G06F13/16
CPC分类号： G06F3/0656 , G06F5/06 , G06F5/065 , G06F5/16 , G06F7/78 , G06F9/544 , G06F13/1673 , G06F17/50 , G06F17/5036 , G06F2003/0691 , G06F2205/062 , G06F2205/063 , G06F2205/066
摘要： A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
摘要翻译：一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。

63. 发明授权

US07773453B2 FIFO peek access 有权
标题翻译： FIFO偷看访问
公开(公告)号：US07773453B2
公开(公告)日：2010-08-10
申请号：US12062780
申请日：2008-04-04
申请人： Jerzy Szwagrzyk , Jeffrey K. Whitt
发明人： Jerzy Szwagrzyk , Jeffrey K. Whitt
IPC分类号： G11C9/00
CPC分类号： G06F5/06 , G06F2205/062
摘要： Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.
摘要翻译：公开了一种FIFO偷窥访问设备，其利用窥视信号访问存储在FIFO中的数据，而不丢失或擦除数据。窥视信号被应用于读取地址逻辑并且防止在窥视地址逻辑中的指针的递增，使得在读使能信号被断言之后，可以在下一个读使能信号上再次访问相同的数据块。

64. 发明申请

US20100180095A1 BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE 审中-公开
标题翻译：缓冲器控制器件和缓冲器存储器件
公开(公告)号：US20100180095A1
公开(公告)日：2010-07-15
申请号：US12095610
申请日：2006-11-28
申请人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
发明人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
IPC分类号： G06F12/14
CPC分类号： G06F5/14 , G06F2205/062
摘要： The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer.
摘要翻译：本发明的缓冲器控制装置包括：保持与读指针不同的虚拟指针和写指针的指针保持单元; 访问控制单元，其控制对环形缓冲器的访问; 判断单元，判断读指针和写指针之一是否达到与虚拟指针所指示的地址基本相同的地址; 以及禁止单元，其在所述读取指针和所述写入指针之一达到与所述虚拟指针所指示的地址基本相同的地址的情况下，使用所述读取指针和所述写入指针中的一者禁止正常访问正常访问由访问控制单元控制，其中访问控制单元进一步控制对环形缓冲器的重新访问。

65. 发明授权

US06865652B1 FIFO with undo-push capability 失效
标题翻译： FIFO具有撤销功能
公开(公告)号：US06865652B1
公开(公告)日：2005-03-08
申请号：US09586575
申请日：2000-06-02
申请人： Jennifer Pencis , Chandrakant Pandya , Sanjiv K. Lakhanpal , Mark D. Nicol
发明人： Jennifer Pencis , Chandrakant Pandya , Sanjiv K. Lakhanpal , Mark D. Nicol
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F5/065 , G06F2205/062
摘要： A plurality of command segments comprising one command are received into an integrated circuit in a plurality of phases, each command segment being received in a different phase. The command segments are pushed into a command queue. Control logic checks for a cancellation indication for the command being received. If a cancellation indication is received, the control logic for the command queue performs an undo-push operation to remove the command segments stored in the command queue associated with the cancelled command.
摘要翻译：包括一个命令的多个命令段被以多个相位接收到集成电路中，每个命令段以不同的相位被接收。命令段被推入命令队列。控制逻辑检查正在接收的命令的取消指示。如果接收到取消指示，则命令队列的控制逻辑执行撤消推送操作，以去除与取消的命令相关联的命令队列中存储的命令段。

66. 发明申请

US20050041450A1 FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation 有权
标题翻译：具有在DDR和SDR操作模式下支持x4N，x2N和xN数据宽度的写和读控制电路的FIFO存储器件
公开(公告)号：US20050041450A1
公开(公告)日：2005-02-24
申请号：US10881985
申请日：2004-06-30
申请人： Jiann-Jeng Duh , Mario Au
发明人： Jiann-Jeng Duh , Mario Au
IPC分类号： G06F5/06 , G06F12/16
CPC分类号： G06F5/06 , G06F2205/062
摘要： First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.
摘要翻译：先进先出（FIFO）存储器件配置为支持以下所有四种FIFO存储器模式：（1）DDR读取DDR读取，（2）DDR写入SDR读取，（3）SDR写入DDR读取和（4）SDR写入SDR读取。这些FIFO存储器件在读取和写入端口上提供灵活的x4N，x2N和xN总线匹配，并且可以在写和读时钟信号的上升沿和下降沿写入和读取数据。还提供自定义标志生成和重传电路，可以有效处理任何宽度的SDR读取模式或任何宽度的DDR读取模式的任何宽度的SDR写入模式的任何宽度的DDR写入模式。

67. 发明申请

US20040019743A1 FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same 失效
标题翻译：其中具有支持隐藏的EDC等待时间和总线匹配的多端口高速缓冲存储器阵列的FIFO存储器件及其操作方法
公开(公告)号：US20040019743A1
公开(公告)日：2004-01-29
申请号：US10612849
申请日：2003-07-03
发明人： Mario Au , Jiann-Jeng Duh , Chuen-Der Lien
IPC分类号： G06F012/00
CPC分类号： G11C7/1075 , G06F5/10 , G06F2205/062 , G06F2205/065
摘要： An integrated circuit memory device includes a quad-port cache memory device and a higher capacity supplemental memory device. These memory devices operate collectively as a high speed FIFO having fast fall through capability and extended data capacity. The FIFO does not require complex arbitration circuitry to oversee reading and writing operations. The supplemental memory device may be an embedded on-chip memory device or a separate off-chip memory device (e.g., DRAM, SRAM). The quad-port cache memory device utilizes a data rotation technique to support bus matching. Error detection and correction (EDC) circuits are also provided to check and correct FIFO read data. The EDC circuits operate without adding latency to FIFO read operations.
摘要翻译：集成电路存储器件包括四端口高速缓冲存储器件和较高容量的补充存储器件。这些存储器件集中地作为具有快速下降能力和扩展数据容量的高速FIFO运行。 FIFO不需要复杂的仲裁电路来监督读写操作。补充存储器件可以是嵌入式片上存储器件或单独的片外存储器件（例如，DRAM，SRAM）。四端口高速缓冲存储器件利用数据旋转技术来支持总线匹配。还提供错误检测和校正（EDC）电路来检查和校正FIFO读取数据。 EDC电路在不增加FIFO读操作的延迟的情况下运行。

68. 发明授权

US06546461B1 Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein 失效
标题翻译：多端口缓存存储器件和其中具有多端口高速缓冲存储器件的FIFO存储器件
公开(公告)号：US06546461B1
公开(公告)日：2003-04-08
申请号：US09721478
申请日：2000-11-22
申请人： Mario Au , Li-Yuan Chen
发明人： Mario Au , Li-Yuan Chen
IPC分类号： G06F1208
CPC分类号： G11C7/1075 , G06F5/10 , G06F2205/062 , G06F2205/065
摘要： A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port. The multiplexer is responsive to at least one path select signal and has a first input electrically coupled to the data output of the data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of the retransmit register. The data output register is responsive to a read address and has a data input electrically coupled to an output of the multiplexer and a data output electrically coupled to the data output port.
摘要翻译： FIFO存储器件包括具有写入端口和读取端口以及四端口高速缓冲存储器件的嵌入式存储器阵列。高速缓冲存储器设备具有单向数据输入端口，单向数据输出端口，电耦合到写入端口的第一嵌入式存储器端口和电耦合到读取端口的第二嵌入式存储器端口。数据输入寄存器，重发寄存器，数据输出寄存器和多路复用器被提供在高速缓存存储器件内。数据输入寄存器响应于写入地址并且具有电耦合到数据输入端口的数据输入和电耦合到第一嵌入式存储器端口的数据输出。重发寄存器响应于重发地址并且具有电耦合到数据输入端口的数据输入。所述多路复用器响应于至少一个路径选择信号，并且具有电耦合到数据输入寄存器的数据输出的第一输入端，电耦合到第二嵌入式存储器端口的第二输入端和电耦合到重传寄存器。数据输出寄存器响应于读取地址并且具有电耦合到多路复用器的输出的数据输入和电耦合到数据输出端口的数据输出。

69. 发明授权

US06538467B2 Multi-access FIFO queue 有权
标题翻译：多访问FIFO队列
公开(公告)号：US06538467B2
公开(公告)日：2003-03-25
申请号：US09933988
申请日：2001-08-20
申请人： Ole Bentz
发明人： Ole Bentz
IPC分类号： G11C700
CPC分类号： G06F5/10 , G06F2205/062
摘要： FIFO queues are provided that enable multiple accesses to data stored in the FIFO queue. Conventional FIFO queues can be augmented by the addition of a “release pointer,” a “repeat signal,” and a “release signal.” A release pointer points to a location in the queue containing a data element that has already been read. As long as the release signal is not asserted, the release pointer does not change while a read pointer is used to read data from the queue. In order to allow the read pointer to go back and reread previously read data, the repeat signal can be asserted. Asserting the repeat signal causes the read pointer to be set to the value of the release pointer. Once the data is no longer needed, the release pointer can be asserted; causing the release pointer to be incremented along with the read pointer. Incrementing the release pointer frees up memory locations so that new data can be stored in them. FIFO queues of the present invention may comprise multiple release pointers, multiple release signals, and multiple repeat signals. FIFO queues of the present invention may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues of the present invention may also comprise multiple read pointers and an input signal for determining which read pointer is used to read data. The present invention can be advantageously utilized, for example, in implementing certain programming constructs more efficiently than can be implemented using FIFO queues of the prior art.
摘要翻译：提供FIFO队列，其能够对存储在FIFO队列中的数据进行多次访问。可以通过添加“释放指针”，“重复信号”和“释放信号”来增加常规FIFO队列。释放指针指向队列中包含已读取的数据元素的位置。只要释放信号不被断言，当读指针用于从队列中读取数据时，释放指针不会改变。为了允许读取指针返回并重新读取先前读取的数据，可以断言重复信号。断言重复信号使读取指针被设置为释放指针的值。一旦不再需要数据，可以断言释放指针; 导致释放指针与读指针一起递增。增加释放指针释放内存位置，以便可以将新数据存储在其中。本发明的FIFO队列可以包括多个释放指针，多个释放信号和多个重复信号。本发明的FIFO队列还可以包括切换信号，其使读取指针用释放指针切换值。本发明的FIFO队列还可以包括多个读指针和用于确定哪个读指针用于读数据的输入信号。本发明可以有利地用于例如比可以使用现有技术的FIFO队列来实现的方案更有效地实现某些编程结构。

70. 发明申请

US20030034797A1 MULTI-ACCESS FIFO QUEUE 有权
标题翻译：多访问FIFO队列
公开(公告)号：US20030034797A1
公开(公告)日：2003-02-20
申请号：US09933988
申请日：2001-08-20
申请人： Micron Technology, Inc.
发明人： Ole Bentz
IPC分类号： H03K019/173
CPC分类号： G06F5/10 , G06F2205/062
摘要： FIFO queues are provided that enable multiple accesses to data stored in the FIFO queue. Conventional FIFO queues can be augmented by the addition of a nullrelease pointer,null a nullrepeat signal,null and a nullrelease signal.null A release pointer points to a location in the queue containing a data element that has already been read. As long as the release signal is not asserted, the release pointer does not change while a read pointer is used to read data from the queue. In order to allow the read pointer to go back and reread previously read data, the repeat signal can be asserted. Asserting the repeat signal causes the read pointer to be set to the value of the release pointer. Once the data is no longer needed, the release pointer can be asserted, causing the release pointer to be incremented along with the read pointer. Incrementing the release pointer frees up memory locations so that new data can be stored in them. FIFO queues of the present invention may comprise multiple release pointers, multiple release signals, and multiple repeat signals. FIFO queues of the present invention may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues of the present invention may also comprise multiple read pointers and an input signal for determining which read pointer is used to read data. The present invention can be advantageously utilized, for example, in implementing certain programming constructs more efficiently than can be implemented using FIFO queues of the prior art.
摘要翻译：提供FIFO队列，其能够对存储在FIFO队列中的数据进行多次访问。可以通过添加“释放指针”，“重复信号”和“释放信号”来增加常规FIFO队列。发布指针指向队列中包含已读取的数据元素的位置。只要释放信号不被断言，当读指针用于从队列中读取数据时，释放指针不会改变。为了允许读取指针返回并重新读取先前读取的数据，可以断言重复信号。断言重复信号使读取指针被设置为释放指针的值。一旦不再需要数据，就可以断言释放指针，导致释放指针与读指针一起递增。增加释放指针释放内存位置，以便可以将新数据存储在其中。本发明的FIFO队列可以包括多个释放指针，多个释放信号和多个重复信号。本发明的FIFO队列还可以包括切换信号，其使读取指针用释放指针切换值。本发明的FIFO队列还可以包括多个读指针和用于确定哪个读指针用于读数据的输入信号。本发明可以有利地用于例如比可以使用现有技术的FIFO队列来实现的方案更有效地实现某些编程结构。

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