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61. 发明公开

EP2583176A2 ERROR DETECTION FOR FILES 审中-公开
标题翻译： FEHLERERKENNUNGFÜRDATEIEN
公开(公告)号：EP2583176A2
公开(公告)日：2013-04-24
申请号：EP11796171.4
申请日：2011-06-03
申请人： Microsoft Corporation
发明人： MILLER, Thomas J. , CARGILLE, Jonathan M. , TIPTON, William R. , VERMA, Surendra
IPC分类号： G06F11/08 , G06F9/06
CPC分类号： G06F11/0772 , G06F11/004 , G06F11/0766 , G06F11/1004 , G06F11/1064 , G06F11/1072 , G06F11/1402 , G06F11/1435 , G06F11/1441 , G06F12/0826 , G06F12/0828 , G06F16/10 , G06F16/178 , G06F2201/82
摘要： Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.
摘要翻译：本文描述的主题的方面涉及文件的错误检测。在方面，在允许更新到干净的文件之前，将文件标记为脏的标记被写入非易失性存储。此后，可以根据需要更新文件。在文件的所有未完成更新和与文件相关联的错误代码都写入存储器之后，可以定期或在其他时间将文件标记为干净。在等待未完成的更新和错误代码写入存储时，如果接收到更新文件的其他请求，则在允许其他请求更新文件之前，该文件可能再次被标记为脏。写入关于文件的清除标志的请求可能会延迟完成。

62. 发明授权

EP0817065B1 Methods and apparatus for a coherence transformer for connecting computer system coherence domains 失效
标题翻译：方法和装置用于Kohärenzumwandler用于连接计算机系统一致性域
公开(公告)号：EP0817065B1
公开(公告)日：2003-09-17
申请号：EP97304519.8
申请日：1997-06-25
申请人： Sun Microsystems, Inc.
发明人： Hagerstein,Erik E , Hill , Mark Donald , Wood , David A.
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/082 , G06F12/0826 , G06F2212/622

63. 发明公开

EP0817063A3 Encoding method for directory state in cache coherent distributed shared memory system 失效
标题翻译：编码的目录状态的方法与相干缓冲器公共的共享存储器系统
公开(公告)号：EP0817063A3
公开(公告)日：1999-01-27
申请号：EP97304387.0
申请日：1997-06-23
申请人： SUN MICROSYSTEMS, INC.
发明人： Guzovskiy, Aleksandr , Zak, Robert C., Jr. , Bromley, Mark
IPC分类号： G06F12/08
CPC分类号： G06F12/0826
摘要： A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line. A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table. The encoder and decoder perform a table look-up to convert between a cache line shared state word and a state value. Each of said cache line tables stores an ordered list of cache line shared state words and their corresponding state values. The ordered list is a list of cache line shared state words that have the most significance to the multi-processor system.

64. 发明公开

EP0817095A3 Extended symmetrical multiprocessor architecture 失效
公开(公告)号：EP0817095A3
公开(公告)日：1998-08-26
申请号：EP97304797.0
申请日：1997-06-30
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagersten, Erik E. , Hill, Mark D. , Singhal, Ashok
IPC分类号： G06F15/16 , G06F13/40
CPC分类号： G06F9/5016 , G06F12/0813 , G06F12/0826 , G06F12/0831 , G06F12/1072 , G06F15/173
摘要： An architecture and memory mapping technique for an extended multiprocessor (XMP) computer system are provided to overcome physical/electrical limitations of single bus architecture while maximizing bus bandwidth utilization. The XMP computer system includes multiple SMP nodes each including an XMP interface and a repeater structure. The SMP nodes are connected to each other by unidirectional point-to-point links. The repeater structure in each SMP node includes an upper level bus coupled to one or more transaction repeaters. Each transaction repeater broadcasts transactions to bus devices attached to separate lower level buses. Transactions originating in a particular SMP node are stored in a queue, whereas transactions originating in other SMP nodes bypass the incoming queue to the bus device. Multiple transactions may be simultaneously broadcast across the point-to-point link connections between the SMP nodes in a defined, uniform order. Each of the n SMP nodes is assigned 1/n of the total address space. Cache coherency information is stored for the memory in each SMP node. Memory regions may be assigned to operate in one of three modes: normal, migratory, or replicate. When operating in normal mode, transaction to an address space assigned to a particular node are tried only locally in that node first. In migratory mode transactions are always sent globally. And in replicate mode duplicate copies of the replicate memory region are assigned to each SMP node so that transactions are always tried locally first, and only sent globally if an improper cache coherency state is returned.

65. 发明公开

EP0851356A2 Multiprocessor computer system 失效
标题翻译： Multiprozessor-Rechnersystem
公开(公告)号：EP0851356A2
公开(公告)日：1998-07-01
申请号：EP97308077.3
申请日：1997-10-13
申请人： NCR INTERNATIONAL INC.
发明人： Young, Gene F. , James, Larry C. , Stevens, Roy M.
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813 , G06F12/082
摘要： The present invention relates to a multiprocessor computer system having comprising a plurality of processors and a memory system including a system memory shared by the plurality of processors together with data cache memories, at least one data cache memory associated with each one of said processors.
The computer system employs a directory based cache coherency scheme for maintaining consistency between lines of data residing in the shared system memory and lines of data residing in the data cache memories. The coherency scheme depends on storing line status information for lines of the shared system memory. The provision for storing line status information comprises a state cache memory associated with the shared system memory to cache the memory line status information. The state cache memory is sized to store status information for a portion only of the memory lines in the shared system memory (e.g. one sixteenth of the memory lines in the shared system memory) and can be a direct mapped cache.
摘要翻译：多处理器计算机系统本发明涉及一种具有多个处理器的多处理器计算机系统和包括由数据高速缓存存储器与多个处理器共享的系统存储器的存储器系统，至少一个与所述处理器中的每一个相关联的数据高速缓冲存储器。计算机系统采用基于目录的高速缓存一致性方案来维持驻留在共享系统存储器中的数据线与驻留在数据高速缓冲存储器中的数据线之间的一致性。一致性方案取决于存储共享系统内存线路的线路状态信息。用于存储线路状态信息的提供包括与共享系统存储器相关联的状态高速缓冲存储器，以缓存存储器线路状态信息。状态高速缓冲存储器的大小设置为仅存储共享系统存储器（例如，共享系统存储器中的存储器线路的十六分之一）中的存储器线路的一部分的状态信息，并且可以是直接映射高速缓存。

66. 发明公开

EP0817065A1 Methods and apparatus for a coherence transformer for connecting computer system coherence domains 失效
标题翻译：方法和装置用于Kohärenzumwandler用于连接计算机系统一致性域
公开(公告)号：EP0817065A1
公开(公告)日：1998-01-07
申请号：EP97304519.8
申请日：1997-06-25
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagerstein,Erik E , Hill , Mark Donald , Wood , David A.
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/082 , G06F12/0826 , G06F2212/622
摘要： An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.
摘要翻译：为促进存储器块的共享，这在计算机节点具有本地的物理地址，所述计算机节点之间和到外部设备的装置。该装置包括窥探构造成用于与计算机节点的公共总线耦合的逻辑。窥探逻辑被配置为监视，当耦合到公共总线，该公共总线上的存储器存取请求。因此，存在包括耦合到所述监视逻辑窥探标签阵列。探听标记阵列包括用于跟踪由外部设备高速缓存的存储块的存储块的第一多个的所有副本的标签。此外，存在被包括耦合到所述监视逻辑用于使得的装置中，当耦合到外部设备，使用适合于与外部设备进行通信的协议的外部设备进行通信的协议转换逻辑。

67. 发明公开

EP0817063A2 Encoding method for directory state in cache coherent distributed shared memory system 失效
标题翻译：编码的目录状态的方法与相干缓冲器公共的共享存储器系统
公开(公告)号：EP0817063A2
公开(公告)日：1998-01-07
申请号：EP97304387.0
申请日：1997-06-23
申请人： SUN MICROSYSTEMS, INC.
发明人： Guzovskiy, Aleksandr , Zak, Robert C., Jr. , Bromley, Mark
IPC分类号： G06F12/08
CPC分类号： G06F12/0826
摘要： A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line.
A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table. The encoder and decoder perform a table look-up to convert between a cache line shared state word and a state value. Each of said cache line tables stores an ordered list of cache line shared state words and their corresponding state values. The ordered list is a list of cache line shared state words that have the most significance to the multi-processor system.
摘要翻译：从处理器通过一个高速缓存行的目录系统ausrichtet高速缓存线的访问请求与共享存储器系统的多处理器系统规定的目录。高速缓存行规定目录存储的状态值没有标识的缓存行的共享状态字。高速缓存行的共享状态字标识处理器确实拥有高速缓存行，每个处理器的访问的状态的确股进入高速缓存行。状态值编码器编码的高速缓存线的共享状态字到状态值并加载状态值到高速缓存线状态的目录。状态值译码器中检索所述高速缓存线的状态值转换成用于由高速缓存行目录系统中使用的高速缓存线的共享状态字进行解码。高速缓存行的表的多个被用于与分配给一个表的每个高速缓存行。该高速缓存线表存储用于存储在所述表中的每个高速缓存线的共享状态字的状态值。该编码器和解码器执行表查找以高速缓存行共享状态字和一个状态值之间进行转换。每个所述高速缓存行的表存储在缓存行的共享状态字和它们对应的状态值有序列表。有序列表的是高速缓存线的共享状态字的列表thathave到多处理器系统中最显着性。

68. 发明公开

EP0460852A3 System for maintaining data coherency between main and cache memories 失效
标题翻译：维护主缓存间数据的系统
公开(公告)号：EP0460852A3
公开(公告)日：1992-08-05
申请号：EP91304798.1
申请日：1991-05-28
申请人： NCR International, Inc.
发明人： Kass, William J. , Hilley, Michael R. , Hoevel, Lee W.
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F2212/622
摘要： A system of maintaining coherency for a data block transferred from a main memory (22) to a cache memory (20) is provided. The data transfer is recorded in a tag register (32) in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory (20) is only notified in the event an overwrite is detected. An invalid flag is then set in the cache memory.

69. 发明公开

EP3217289A3 SYSTEM AND METHOD FOR PREVENTING CACHE CONTENTION 审中-公开
标题翻译：用于防止高速缓存污染的系统和方法
公开(公告)号：EP3217289A3
公开(公告)日：2018-01-10
申请号：EP17159439.3
申请日：2017-03-06
申请人： Ceva D.S.P. Ltd.
发明人： Rohe, Amos , Sadeh, Roni
IPC分类号： G06F12/0864 , G06T1/60 , G06F12/0875
CPC分类号： G06F12/1483 , G06F9/30036 , G06F12/0826 , G06F12/0853 , G06F12/0864 , G06F12/0875 , G06F2212/1032 , G06F2212/1041 , G06F2212/1044 , G06F2212/1052 , G06F2212/6026 , G06F2212/622 , G06T1/60
摘要： A system and method for preventing cache contention for a cache including a plurality of ways and a separate port for each way, the method including: obtaining, in a core of a processor, a multidimensional coefficient array of a multidimensional filter, and pointers to data elements from a plurality of rows of a multidimensional data array, and loading the plurality of rows into the cache, where each row is stored in a different way of the cache.
摘要翻译：本发明公开了一种用于防止高速缓存的高速缓存争用的系统和方法，所述高速缓存包括用于每个路的多个路和单独的端口，所述方法包括：在处理器的核中获得多维滤波器的多维系数阵列和指向数据的指针来自多维数据阵列的多行的元素，并且将多个行加载到高速缓存中，其中每行以高速缓存的不同方式存储。

70. 发明公开

EP2583176A4 ERROR DETECTION FOR FILES 审中-公开
标题翻译： FEHLERERKENNUNGFÜRDATEIEN
公开(公告)号：EP2583176A4
公开(公告)日：2017-10-04
申请号：EP11796171
申请日：2011-06-03
申请人： MICROSOFT TECHNOLOGY LICENSING LLC
发明人： MILLER THOMAS J , CARGILLE JONATHAN M , TIPTON WILLIAM R , VERMA SURENDRA
IPC分类号： G06F11/08 , G06F11/14 , G06F17/30
CPC分类号： G06F11/0772 , G06F11/004 , G06F11/0766 , G06F11/1004 , G06F11/1064 , G06F11/1072 , G06F11/1402 , G06F11/1435 , G06F11/1441 , G06F12/0826 , G06F12/0828 , G06F17/30067 , G06F17/30174 , G06F2201/82
摘要： Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.
摘要翻译：这里描述的主题的各方面涉及文件的错误检测。在各方面，在允许更新干净文件之前，将标记文件为脏的标志写入非易失性存储器。此后，文件可以根据需要更新。在文件的所有未完成更新和与该文件关联的错误代码写入存储之后，可能会定期或在某个其他时间将该文件标记为干净。在等待未完成更新和错误代码写入存储器的过程中，如果接收到更新文件的附加请求，则可以在允许附加请求更新文件之前再次将该文件标记为脏。可以懒惰地完成关于写入文件干净标志的请求。

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