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61. 发明申请

WO1995002897A1 CHEMICAL VAPOR DEPOSITION PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS 审中-公开
标题翻译：用于制备层状超导材料的化学气相沉积工艺
公开(公告)号：WO1995002897A1
公开(公告)日：1995-01-26
申请号：PCT/US1994007402
申请日：1994-06-30
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , PAZ DE ARAUJO, Carlos, A. , WATANABE, Hitoshi , SCOTT, Michael, C. , MIHARA, Takashi
IPC分类号： H01L21/316
CPC分类号： C23C16/45561 , C23C16/0218 , C23C16/40 , C23C16/56 , C30B7/00 , C30B7/005 , C30B25/02 , C30B29/68 , H01C7/1013 , H01L21/02197 , H01L21/02271 , H01L21/02337 , H01L21/02356 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A substrate (17) is prebaked (412) in an oxygen furnace. A thin film (60) of layered superlattice oxide is formed on the substrate (17) by a chemical vapor deposition process (420). The film (60) is RTP baked (424) to provide grains with a mixed phase of A-axis and C-axis orientation. The film (60) may be treated by ion implantation (422) prior to the RTP bake (424) and oxygen furnace annealed (426) after the RTP bake. An electrode (77) is deposited on the layered superlattice thin film (60) and then the film and electrode are oxygen furnace annealed (432).
摘要翻译：将衬底（17）在氧炉中预烘烤（412）。通过化学气相沉积工艺（420）在衬底（17）上形成层状超晶格氧化物薄膜（60）。膜（60）是RTP烘烤（424），以提供具有A轴和C轴取向的混合相的晶粒。在RTP烘烤之前，可以在RTP烘烤（424）和氧炉退火（426）之前通过离子注入（422）处理膜（60）。在层状超晶格薄膜（60）上沉积电极（77），然后将膜和电极进行氧炉退火（432）。

62. 发明申请

WO1995002883A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：WO1995002883A1
公开(公告)日：1995-01-26
申请号：PCT/US1994007403
申请日：1994-06-30
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric, non-volatile memory (336) includes a constant voltage source (85), a bit line (79), a memory cell (70) having a first ferroelectric capacitor (76) connected between the bit line (79) and the constant voltage source (85), a source (105) of a reference voltage, and a latch (74) connected between the bit line (79) and the reference voltage source (105). The latch (74) drives the bit line (79) to the same logic state as the ferroelectric capacitor (76) to read and rewrite the capacitor (76) in a single operation. The reference voltage is between QI/CD and QSW/CD + QI/CD, where QI is the linear capacitance of said first ferroelectric capacitor (76), CD is the capacitance of said bit line (79), and QSW is the switching charge of said first ferroelectric capacitor (76). In one embodiment, the reference voltage is provided by a ferroelectric dummy capacitor (141) having an area smaller than the area of the first capacitor (128) but greater than 1/2 the area of the first capacitor (128).
摘要翻译：铁电非易失性存储器（336）包括恒压源（85），位线（79），存储单元（70），其具有连接在所述位线（79）和所述第一铁电电容器恒压源（85），参考电压源（105）和连接在位线（79）和参考电压源（105）之间的锁存器（74）。锁存器（74）将位线（79）驱动到与铁电电容器（76）相同的逻辑状态，以便在单次操作中读取和重写电容器（76）。参考电压在QI / CD和QSW / CD + QI / CD之间，其中QI是所述第一铁电电容器（76）的线性电容，CD是所述位线（79）的电容，QSW是开关电荷的所述第一铁电电容器（76）。在一个实施例中，参考电压由具有小于第一电容器（128）的面积但大于第一电容器（128）的面积的1/2的铁电虚拟电容器（141）提供。

63. 发明申请

WO1993012542A1 LAYERED SUPERLATTICE MATERIAL APPLICATIONS 审中-公开
标题翻译：层叠超级材料应用
公开(公告)号：WO1993012542A1
公开(公告)日：1993-06-24
申请号：PCT/US1992010627
申请日：1992-12-08
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , PAZ DE ARAUJO, Carlos, A. , CUCHIARO, Joseph, D. , SCOTT, Michael, C. , McMILLAN, Larry, D.
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01C7/1013 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： An integrated circuit (36) includes a layered superlattice material (60, 60', 92) having formula (1), where A1, A2 ... Aj represent A-site elements (84) in a perovskite-like structure, S1, S2 ... Sk represent superlattice generator elements (87), B1, B2 ... Bl represent B-site elements (86) in a perovskite-like structure (94), Q represents an anion (88), the superscripts indicate the valences of the respective elements (84, 87, 86, 88) the subscripts indicate the number of atoms of the element in the unit cell (89), and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories (36). Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories (36).
摘要翻译：集成电路（36）包括具有公式（1）的分层超晶格材料（60,60'，92），其中A1，A2 ... Aj表示钙钛矿型结构的A位元素（84），S1， S2 ... Sk表示超晶格发生元件（87），B1，B2 ... B1表示钙钛矿型结构（94）中的B位元素（86），Q表示阴离子（88），上标表示各元素（84,87,86,88）的化合价指示单元中元素的原子数（89），并且至少w1和y1不为零。这些材料中的一些是非常低的疲劳铁电体，并且被应用在非易失性存储器中（36）。其他的是高介电常数材料，它们在长期使用中不会降解或击穿，并被应用在易失性存储器中（36）。

64. 发明公开

EP0954031A3 Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and including a hydrogen barrier layer, and method for fabricating the same 审中-公开
标题翻译：与氢接触的低灵敏度，具有氢阻挡层的铁电集成电路和其制造方法
公开(公告)号：EP0954031A3
公开(公告)日：2009-09-02
申请号：EP99102684.0
申请日：1999-02-12
申请人： SYMETRIX CORPORATION , NEC CORPORATION
发明人： Cuchiaro, Joseph D. , Feruya, Akira , Paz de Araujo, Carlos A. , Miyasaka, Yoichi
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/11585 , H01L27/1159 , H01L28/55 , H01L28/75
摘要： A hydrogen barrier layer (128) is formed above a ferroelectric thin film (124) in an integrated circuit. The hydrogen barrier layer (128) is directly over a protected segment (123) of the ferroelectric thin film (124), while a sacrificial segment (125) of the ferroelectric thin film (124) extends laterally beyond the edges (129) of the hydrogen barrier layer (128). The sacrificial segment (125) absorbs hydrogen so that it cannot diffuse laterally into the protected segment (123) of the ferroelectric thin film (124). After it absorbs hydrogen, the sacrificial segment (125) is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film (124) preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate material helps to reduce hydrogen degradation of the ferroelectric properties.

65. 发明授权

EP1018151B1 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME WITHOUT EXPOSURE TO OXYGEN 失效
标题翻译：生产的层状的 - 超晶格 - 材料氧气的排除
公开(公告)号：EP1018151B1
公开(公告)日：2004-09-01
申请号：EP98934436.1
申请日：1998-07-17
申请人： SYMETRIX CORPORATION , Infineon Technologies AG
发明人： SCHINDLER, Gunther , HARTNER, Walter , MAZURE, Carlos , SOLAYAPPAN, Narayan , JOSHI, Vikram , DERBENWICK, Gary, F.
IPC分类号： H01L21/316
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1275 , C23C18/1283 , C23C18/1295

66. 发明公开

EP1003208A3 Integrated circuit having self-aligned hydrogen barrier layer and method for fabricating same 审中-公开
标题翻译：具有自对准Wasserstoffbariereschicht及其制造方法集成电路
公开(公告)号：EP1003208A3
公开(公告)日：2003-06-11
申请号：EP99122247.2
申请日：1999-11-08
申请人： SYMETRIX CORPORATION , NEC Corporation
发明人： Cuchiaro, Joseph D. , Paz de Araujo, Carlos A. , Furuya, Akira, c/o NEC Corporation , Miyasaka, Yoichi,c/o NEC Corporation
IPC分类号： H01L21/28 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： In an integrated circuit, a stack of thin film (124) layers comprising respectively a bottom electrode (122), a thin film (124) of metal oxide, a top electrode (126), a lower barrier-adhesion layer (128), a hydrogen barrier layer (130), and an upper barrier-adhesion layer (132) are patterned to form a memory capacitor (120) capped with a self-aligned hydrogen barrier layer (130). Preferably, the top and bottom electrodes comprise platinum, the metal oxide material comprises ferroelectric layered superlattice material, the upper and lower barrier-adhesion layers comprise titanium, and the hydrogen barrier layer (130) comprises titanium nitride. The hydrogen barrier layer (130) inhibits diffusion of hydrogen, thereby preventing hydrogen degradation of the metal oxides. Part of the upper barrier-adhesion layer (132) is removed in order to increase the electrical conductivity in the layer. Preferably, the memory capacitor is a ferroelectric nonvolatile memory. Preferably, the layered superlattice material includes strontium bismuth tantalate or strontium bismuth tantalum niobate.

67. 发明授权

EP0770265B1 METHOD OF FORMING DOPED BST LAYERS AND INTEGRATED CIRCUIT CAPACITORS COMPRISING MAGNESIUM DOPED BST LAYERS 失效
标题翻译：用于生产掺杂BST-层和电容器用镁掺杂层BST集成电路的
公开(公告)号：EP0770265B1
公开(公告)日：2002-03-27
申请号：EP95926640.4
申请日：1995-07-10
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： AZUMA, Masamichi , PAZ DE ARAUJO, Carlos, A. , SCOTT, Michael, C. , CUCHIARO, Joseph, D.
IPC分类号： H01L21/3205 , H01L27/115 , H01L21/316
CPC分类号： H01L27/11502 , C04B35/4682 , C04B35/6264 , C04B2235/3213 , C04B2235/3224 , C04B2235/3227 , C04B2235/3229 , C04B2235/3243 , C04B2235/3268 , C04B2235/441 , C04B2235/449 , C04B2235/72 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1275 , C23C18/1295 , C23C18/14 , C30B7/00 , C30B29/68 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A magnesium doped metal oxide layer in an integrated circuit is made by providing a liquid precursor comprising a first metal, a second metal and magnesium, applying the precursor to a substrate, and treating the precursor to form said magnesium doped metal oxide layer on the substrate. In one embodiment the liquid precursor comprises a mixture of a BST solution and a dopant solution of magnesium carboxylate. The precursor is spun (P45) on the substrate, for example a first electrode, dried (P46) at 400 DEG C for 2 minutes then annealed (P47) at 750 DEG C to 800 DEG C for about an hour to form a BST layer accurately doped with magnesium.

68. 发明授权

EP0769206B1 THIN FILMS OF ABO3 WITH EXCESS A-SITE AND B-SITE MODIFIERS AND METHOD OF FABRICATING INTEGRATED CIRCUITS WITH SAME 失效
标题翻译：过剩-A型和B型ELEMENTS AND METHOD集成电路的使用本LAYERS的TYPE ABO.sub.3薄层
公开(公告)号：EP0769206B1
公开(公告)日：2002-03-27
申请号：EP95925422.8
申请日：1995-06-30
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： AZUMA, Masamichi , PAZ DE ARAUJO, Carlos, A. , SCOTT, Michael, C.
IPC分类号： H01L21/3205 , H01L27/115 , H01L21/316
CPC分类号： H01L27/11502 , C23C18/1216 , C23C18/1295 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A method for fabricating an integrated circuit capacitor (10, 20, 30) having a dielectric layer (15, 26, 37) comprising BST with excess A-site and B-site materials such as barium and titanium added. An organometallic or metallic soap precursor solution is prepared (P42) comprising a stock solution of BST of greater than 99.999 % purity blended with excess A-site and B-site materials such as barium and titanium such that the barium is in the range of 0.01-100 mol %, and such that the titanium is in the range of 0.01-100 mol %. A xylene exchange (P44) is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor solution is spun on a first electrode (P45), dried (P46) at 400 °C for 2 to 10 minutes, then annealed (P47) at 650 °C to 800 °C for about an hour to form a layer of BST with excess titanium. A second electrode is deposited (P48), patterned (P49), and annealed at between 650 °C to 800 °C for about 30 minutes. The resultant capacitor (10, 20, 30) exhibits an enlarged dielectric constant with little change in leakage current.

69. 发明授权

EP0699343B1 THIN FILM CAPACITORS ON GALLIUM ARSENIDE SUBSTRATE AND PROCESS FOR MAKING THE SAME 失效
标题翻译：薄膜电容器关于砷化镓衬底和方法
公开(公告)号：EP0699343B1
公开(公告)日：2001-09-12
申请号：EP95912921.4
申请日：1995-03-16
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： AZUMA, Masamichi , PAZ DE ARAUJO, Carlos, A. , SCOTT, Michael, C. , UEDA, Toshiyuki
IPC分类号： H01L21/3205
CPC分类号： C23C18/1225 , C23C18/1216 , H01L21/31691 , H01L28/55
摘要： A silicone nitride barrier layer (12) is deposited on a gallium arsenide substrate (11) to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer (14) is deposited on the barrier layer. A first electrode (16) comprising an adhesion layer (18) and a second layer (20) is formed on the stress reduction layer. An essentially anhydrous alkoxycarboxylate liquid precursor is prepared, just before use a solvent exchange step is performed, then the precursor is spun on the first electrode, dried at 400 °C, and annealed at between 600 °C and 850 °C to form a BST capacitor dielectric (22). A second electrode (24) is deposited on the dielectric and annealed.

70. 发明公开

EP1032724A1 METHOD AND APPARATUS FOR MISTED DEPOSITION OF THIN FILMS 审中-公开
标题翻译：方法和设备的薄膜雾生产
公开(公告)号：EP1032724A1
公开(公告)日：2000-09-06
申请号：EP98957683.0
申请日：1998-11-09
申请人： SYMETRIX CORPORATION , Primaxx, Inc.
发明人： SOLAYAPPAN, Narayan , GRANT, Robert, W. , MCMILLAN, Larry, D. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： C23C16/44 , C23C16/40 , H01L21/314
CPC分类号： C23C18/12 , B05D1/007 , B05D1/04 , C23C16/40 , C23C16/448 , C23C16/45561 , C23C16/45565 , C23C18/1216 , H01L21/31691 , H01L28/55
摘要： A liquid mass flow controller (15) controls the delivery of a precursor to a mist generator (12). The precursor is misted utilizing a venturi (460) in which a combination of oxygen and nitrogen gas is charged by a corona wire (328) and passes over a precursor-filled throat (466). The particle size of the mist is reduced in a mist refiner (302), passes into a velocity reduction chamber (636), and then flows into a deposition chamber (632) through inlet ports (688) in a mist inlet plate (682) that is both a partition between the chambers and a grounded upper electrode. The inlet plate (682) is located above and substantially parallel to the plane of the substrate (600) on which the mist is to be deposited. An accelerator (18) accelerates the charged mist particles in an electric field between the upper electrode and the lower electrode towards the substrate (600). The residual mist is withdrawn from the deposition chamber (632) via an exhaust port (642).

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