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61. 发明授权

US5432727A Apparatus for computing a sticky bit for a floating point arithmetic unit 失效
标题翻译：用于计算浮点运算单元的粘性位的装置
公开(公告)号：US5432727A
公开(公告)日：1995-07-11
申请号：US725417
申请日：1991-07-01
申请人： Sadar U. Ahmed
发明人： Sadar U. Ahmed
IPC分类号： G06F7/485 , G06F7/50 , G06F7/38
CPC分类号： G06F7/485 , G06F7/49952
摘要： An arithmetic unit wherein a plurality of electrical signals corresponding to the mantissa is shifted and a bit signal corresponding to the sticky bit is calculated simultaneously with the calculation of the shift count. Initially, a serial approach to mantissa shifting and sticky bit calculation is employed. A parallel approach to matissa shifting and sticky bit calculation is adopted when all shift count bits are available. In one embodiment of the present invention, an exclusive OR gate is used to calculate the difference between the least significant bits of the first and second exponents. A shifter/sticky bit calculator immediately acts upon the output of the exclusive OR gate and begins shifting the mantissa and calculating the guard, round, and sticky bits. The more significant bits of the shift count are progressively generated thereafter, and the guard, round and sticky bits are calculated and the mantissa is shifted as the shift count bits become available. As soon as all shift count bits are available, a parallel approach to sticky bit calculation is adopted. Consequently, the shifted mantissa and the guard, round and sticky bits are available at the same time and much earlier than if the sticky bit were calculated according to known methods.
摘要翻译：运算单元，其中对应于尾数的多个电信号被移位，并且与移位计数的计算同时计算与粘滞位对应的位信号。首先，采用串尾方法进行尾数移位和粘性位计算。当所有移位计数位都可用时，采用并行方法进行matissa移位和粘滞位计算。在本发明的一个实施例中，使用异或门来计算第一和第二指数的最低有效位之间的差。立即对移位器/粘滞位计算器进行异或门的输出，并开始移动尾数并计算保护，圆和粘位。随后逐渐生成移位计数的更高有效位，并且计算保护，圆和粘比特，并且随着移位计数位变为可用，尾数被移位。一旦所有的移位计数位都可用，就采用并行的粘滞位计算方法。因此，如果按照已知方法计算粘性位，移位的尾数和保护，圆形和粘性位可以同时获得，并且早得多。

62. 发明授权

US5280370A Apparatus and method for scanning by means of a rotatable detector array 失效
标题翻译：通过可旋转检测器阵列进行扫描的装置和方法
公开(公告)号：US5280370A
公开(公告)日：1994-01-18
申请号：US577865
申请日：1990-09-05
申请人： Hans W. Faust , Karl Felle , Dierk Hobbie , Heinz Krastel , Richard J. Kaiser , Robert L. Kuelthau , Alward J. Pinard , Gary D. Wylie
发明人： Hans W. Faust , Karl Felle , Dierk Hobbie , Heinz Krastel , Richard J. Kaiser , Robert L. Kuelthau , Alward J. Pinard , Gary D. Wylie
IPC分类号： H04N1/04 , H04N1/10 , H04N1/191 , H04N1/407
CPC分类号： H04N1/128 , H04N1/04 , H04N1/1008 , H04N1/1911 , H04N1/4078 , H04N2201/0432 , H04N2201/044
摘要： An apparatus for capture of image data from an object has a detector array containing at least one detector row, and arrangements for rotating the detector array relative to the object, as well as for moving the object and the detector array relative to one another in a desired direction of scan. A control arrangement causes the detector array to be rotated to a desired orientation with respect to the object based on information in the object and causes the object to be scanned by the detector array in such a way that the detector row is at right angles to the direction of scan. A similar method is also provided.
摘要翻译：在根据本发明的方法中，首先通过包含在待评估对象中的信息项来定义后续扫描的方向。然后，用于数据拾取的检测器阵列以这样的方式旋转，使得其检测器行垂直于扫描方向。扫描方向的选择可以是自动的还是互动的。对于实际的数据拾取，物体在固定式检测器阵列上以条形格式定义的扫描方向移动。在该处理期间由检测器阵列产生的信号在随后的处理器中进行评估。

63. 发明授权

US5274473A Rapid variable angle digital screening 失效
标题翻译：快速变角数字筛选
公开(公告)号：US5274473A
公开(公告)日：1993-12-28
申请号：US809032
申请日：1991-12-16
申请人： Robert C. Kidd , J. Brett Lefebvre
发明人： Robert C. Kidd , J. Brett Lefebvre
IPC分类号： H04N1/405 , H04N1/40 , H04N1/00
CPC分类号： H04N1/4058
摘要： A method for reproducing images using rotated screens, wherein the rotated screens are formed by the replication of a screen tile (ABCD). The screen tile (ABCD) is based on a seed screen cell (11, 17) that is disposed at the desired angle of screen rotation, theta, and is replicated so as to fill the screen tile. Thus, the screen can be generated by replicating the screen tile with respect to the same coordinate system as that identifying addresses for the image data being screened, i.e., without rotating the screen tile. Both the screen tile and the seed screen cell (11, 17) are represented by matrices. Noise (51) can be introduced into process of forming the screen in order to further lessen Moire patterns.
摘要翻译：一种使用旋转屏幕再现图像的方法，其中旋转屏幕通过屏幕瓦片（ABCD）的复制形成。屏幕瓦片（ABCD）基于以屏幕旋转θ所需的角度设置的种子屏幕单元（11,17），并且被复制以填充屏幕瓦片。因此，可以通过相对于与被屏蔽的图像数据的识别地址相同的坐标系复制屏幕图块，即不旋转屏幕图块来生成屏幕。屏幕瓦片和种子屏幕单元（11,17）都由矩阵表示。可以将噪声（51）引入到形成屏幕的过程中，以进一步减少莫尔图案。

64. 发明授权

US5091846A Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency 失效
标题翻译：缓存提供用于虚拟地址的缓存/非缓存写入和复制模式，并包括总线侦听以维护一致性
公开(公告)号：US5091846A
公开(公告)日：1992-02-25
申请号：US428480
申请日：1989-10-30
申请人： Howard G. Sachs , James Y. Cho
发明人： Howard G. Sachs , James Y. Cho
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0804
摘要： A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags. Upon initialization of the modifiable translation logic in the cache-memory management system, the address translations and associated system tags are loaded into the address translation logic of the cache-memory management system. Thereafter, as a part of the virtual to real address translation performed by the cache-memory management system, access modes and attributes are determined for each address translation, to provide for proper memory access of cacheable versus non-cacheable storage, etc., as part of the address translation and memory management function.
摘要翻译：具有高速缓存存储器管理系统的计算系统为可寻址存储器提供可选择的访问模式，提供可定位在固定页边界基础上的可高速缓存和不可访问的访问模式。各种访问模式可以在缓存存储器管理系统的翻译逻辑中逐页地混合。高速缓存存储器管理系统提供高速虚拟到实际地址转换以及定义访问优先级的关联系统标签数据和与每个相应地址转换相关联的访问模式。可选择的访问模式提供软件可定义的功能，例如可缓存数据或不可缓存数据，用于可缓存数据的直写或副本主存储器更新策略，以及实时存储器地址空间选择作为主存储器实际地址空间，而不是Boot ROM实地址空间与输入/输出实际地址空间。页表加载到包含地址转换数据和关联系统标签的主存储器中。在高速缓冲存储器管理系统中的可修改的翻译逻辑初始化之后，将地址转换和相关联的系统标签加载到高速缓存存储器管理系统的地址转换逻辑中。此后，作为由高速缓冲存储器管理系统执行的虚拟到实际地址转换的一部分，为每个地址转换确定访问模式和属性，以提供可高速缓存与不可缓存存储等的适当存储器访问，如部分地址转换和内存管理功能。

65. 发明授权

US4985779A Improved method and apparatus for generating halftone images 失效
标题翻译：改进的产生半色调图像的方法和装置
公开(公告)号：US4985779A
公开(公告)日：1991-01-15
申请号：US409114
申请日：1989-09-19
申请人： Winrich Gall
发明人： Winrich Gall
IPC分类号： H04N1/40 , H04N1/405
CPC分类号： H04N1/40087 , H04N1/4058
摘要： An improved method and apparatus for generating halftone images using a beam of variable intensity. A look-up table that is accessed, at a minimum, by position coordinates and image intensity data provides beam intensity information. In certain embodiments, the look-up table may be accessed by dot set identification data and/or randomly generated numbers in addition to the position coordinates and the image intensity data. The position coordinates (x,y) may be generated by performing a coordinate transformation on the beam position coordinates (u,v). The beam intensity data stored in the look-up table may permit the formation of soft dots, i.e. halftone dots that are formed by different levels of beam exposure. The look-up table also permits an increase in dot frequency in the middle tones.
摘要翻译：一种用于使用可变强度的光束产生半色调图像的改进的方法和装置。通过位置坐标和图像强度数据访问的查找表提供了光束强度信息。在某些实施例中，除了位置坐标和图像强度数据之外，可以通过点集识别数据和/或随机生成的数字来访问查找表。可以通过对光束位置坐标（u，v）执行坐标变换来生成位置坐标（x，y）。存储在查找表中的光束强度数据可以允许形成软点，即由不同程度的束曝光形成的半色调点。查找表还允许在中间色调中增加点频率。

66. 发明授权

US4933835A Apparatus for maintaining consistency of a cache memory with a primary memory 失效
标题翻译：用于保持高速缓冲存储器与主存储器的一致性的装置
公开(公告)号：US4933835A
公开(公告)日：1990-06-12
申请号：US300174
申请日：1989-01-19
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.
摘要翻译：公开了一种具有用于耦合系统元件的高速系统总线的微处理器系统，并且具有分别连接到可独立操作的指令和数据高速缓存-UUU的单独的超高速指令和数据高速缓存-MMU接口的双总线微处理器。主存储器耦合到系统总线，用于选择性地存储和输出数字信息。指令和数据高速缓存MMU经由系统总线耦合到主存储器，用于独立地将数字信息存储并输出到相应的可映射的可寻址的非常高速的高速缓冲存储器。微处理器分别通过单独和独立的非常高速的指令和数据总线耦合到指令高速缓存-MMU和数据高速缓存-MUU中的每一个，用于响应于从指令高速缓冲存储器MMU接收的指令来处理从数据高速缓存MMU接收的数据。 MMU。指令总线和数据总线是独立的并且彼此独立，并且允许同时进行非常高速的传输。数据高速缓存-MMU和指令高速缓存-MUU各自具有单独的专用系统总线接口，用于耦合到主存储器和耦合到系统总线的其它外围设备。许多其他系统元件也可以耦合到系统总线，包括中断控制器，I / O处理器，总线仲裁器，阵列处理器和其它外围控制器设备。

67. 发明授权

US4884197A Method and apparatus for addressing a cache memory 失效
标题翻译：用于寻址缓存的方法和装置
公开(公告)号：US4884197A
公开(公告)日：1989-11-28
申请号：US915319
申请日：1986-10-03
申请人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
发明人： Howard G. Sachs , James Y. Cho , Walter H. Hollingsworth
IPC分类号： G06F12/08
CPC分类号： G06F12/0848
摘要： A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface, and an execution unit. The instruction interface controls communications with the external instruction cache and couples the instructions from the instruction cache to the microprocessor at very high speed. The data interface controls communications with the external data cache and communicates data bidirectionally at very high speed between the data cache and the microprocessor. The execution unit selectively processes the data received via the data interface from the data cache responsive to the execution unit decoding and executing a respective one of the instructions received via the instruction interface from the instruction cache. In one embodiment, the external instruction cache is comprised of a program counter and addressable memory for outputting stored instructions responsive to its program counter and to an instruction cache advance signal output from the instruction interface. Circuitry in the instruction interface selectively outputs an initial instruction address for storage in the instruction cache program counter responsive to a context switch or branch, such that the instruction interface repetitively couples a plurality of instructions from the instruction cache to the microprocessor responsive to the cache advance signal, independent of and without the need for any intermediate or further address output from the instruction interface to the instruction cache except upon the occurrence of another context switch or branch.
摘要翻译：公开了一种具有单独的非常高速度的指令和数据接口电路的微处理器架构，用于经由相应的单独的非常高速的指令和数据接口总线耦合到相应的外部指令高速缓存和数据高速缓微处理器由指令接口，数据接口和执行单元构成。指令接口控制与外部指令高速缓存的通信，并以非常高的速度将指令从指令高速缓存耦合到微处理器。数据接口控制与外部数据缓存的通信，并以非常高的速度在数据高速缓存和微处理器之间双向传送数据。响应于执行单元解码，执行单元选择性地处理经由数据接口从数据高速缓存接收的数据，并且执行经由指令接口从指令高速缓存接收的相应指令。在一个实施例中，外部指令高速缓存由程序计数器和可寻址存储器组成，用于响应于其程序计数器输出存储的指令，以及从指令接口输出的指令高速缓存提前信号。响应于上下文切换或分支，指令接口中的电路有选择地输出用于存储在指令高速缓存程序计数器中的初始指令地址，使得指令接口响应于高速缓存提前将多条指令从指令高速缓存耦合到微处理器信号，独立于且不需要从指令接口输出到指令高速缓存的任何中间或另外的地址，除了发生另一个上下文切换或分支之外。

68. 发明授权

US4334124A Floating coordinate system 失效
标题翻译：浮动坐标系
公开(公告)号：US4334124A
公开(公告)日：1982-06-08
申请号：US134345
申请日：1980-03-26
申请人： Bruce E. Imsand , Robert L. Kuehlthau
发明人： Bruce E. Imsand , Robert L. Kuehlthau
IPC分类号： G06F3/033 , G06F3/046 , G08C21/00
CPC分类号： G06F3/046
摘要： Apparatus for determining the position of a cursor with respect to a floating coordinate system, such as a menu. The floating menu incorporates two sensing devices similar to that in the cursor. A processing unit determines the position of the two sensing devices and the position of the cursor with respect to a fixed coordinate system. From this data the position of the cursor with respect to the floating menu is determined.
摘要翻译：用于确定光标相对于诸如菜单的浮动坐标系的位置的装置。浮动菜单包含与光标相似的两个感测设备。处理单元确定两个感测装置的位置和光标相对于固定坐标系的位置。从该数据中确定光标相对于浮动菜单的位置。

69. 发明公开

US20240205642A1 SYNCHRONIZATION/RESYNCHRONIZATION OF DATA ASSETS BASED ON ENTERING A WIRELESS DEAD ZONE GEOFENCE 审中-公开
公开(公告)号：US20240205642A1
公开(公告)日：2024-06-20
申请号：US18084846
申请日：2022-12-20
申请人： Intergraph Corporation
发明人： Javier Buzzalino , Julio P. Roque , Peng Tang
IPC分类号： H04W4/021 , H04L67/1095
CPC分类号： H04W4/021 , H04L67/1095
摘要： Synchronization and resynchronization includes monitoring location of a mobile device relative to a dead zone geofence boundary volume map including a geofence boundary, a dead zone volume, and a buffer zone defining a zone in which the wireless communication service is available for mobile device communication with a server system; determining that the mobile device is approaching or crossing the geofence boundary into the buffer zone toward the dead zone volume; determining data asset(s) that will be needed by the mobile device within the dead zone volume; automatically transmitting the data asset(s) to the mobile device while the mobile device is within the buffer zone; determining that the mobile device has subsequently entered the buffer zone from the dead zone volume; and automatically resynchronizing offline data stored locally by the mobile device while in the dead zone volume with corresponding data stored on the server system.

70. 发明申请

US20230047692A1 CLOUD-BASED SYSTEMS FOR OPTIMIZED MULTI-DOMAIN PROCESSING OF INPUT PROBLEMS USING A SERVERLESS REQUEST MANAGEMENT ENGINE NATIVE TO A SERVER CLOUD INFRASTRUCTURE 有权
公开(公告)号：US20230047692A1
公开(公告)日：2023-02-16
申请号：US17675454
申请日：2022-02-18
申请人： Intergraph Corporation
发明人： Julio P. Roque , Javier Buzzalino , Gregory Louis Bondy , Srinivas Kodali
IPC分类号： G06F9/54
摘要： Various embodiments of the present disclosure provide methods, apparatuses, systems, computing devices, computing entities, and/or the like for determining optimized solutions to input problems in a containerized, cloud-based (e.g., serverless) manner. In one embodiment, an example method is provided. The method comprises: receiving a problem type of an input problem originating from a client computing entity; mapping the problem type to one or more selected solver types; generating one or more container instances of one or more compute containers, each compute container corresponding to a selected solver type; generating a problem output using the one or more container instances; and providing the problem output comprising a solution to the input problem to the client computing entity. In various embodiments, optimized solutions for input problems are determined using a cloud-based multi-domain solver system configured to dynamically allocate computing and processing resources between different solution-determining tasks.

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