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61. 发明授权

US07482865B2 Systems and methods for correcting errors resulting from component mismatch in a feedback path 有权
标题翻译：用于校正由反馈路径中的组件不匹配引起的错误的系统和方法
公开(公告)号：US07482865B2
公开(公告)日：2009-01-27
申请号：US11672331
申请日：2007-02-07
申请人： Michael A. Kost , Jack B. Andersen , Daniel L. W. Chieng
发明人： Michael A. Kost , Jack B. Andersen , Daniel L. W. Chieng
IPC分类号： H03F3/38
CPC分类号： H03F3/2173 , H03F1/30 , H03F1/34 , H03F2200/03 , H03F2200/351
摘要： Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.
摘要翻译：用于使数字PWM放大器反馈回路的反馈路径中的组件不匹配导致性能下降最小化的系统和方法。一个实施例包括具有反馈的数字脉宽调制（PWM）放大器。放大子系统接收数字音频信号并产生模拟输出信号。反馈回路基于滤波的模拟输出信号产生反馈信号，并且基于反馈信号修改数字音频信号。反馈回路包括被配置为过滤模拟输出信号的滤波器和被配置为校正由滤波器引入的元件失配误差的校正电路。在一个实施例中，校正电路接收电源电压的测量，将测量的电压乘以增益，并将缩放的测量值加到反馈信号上，以校正组件失配误差。

62. 发明授权

US07362254B2 Systems and methods for minimizing delay in a control path 有权
标题翻译：用于最小化控制路径延迟的系统和方法
公开(公告)号：US07362254B2
公开(公告)日：2008-04-22
申请号：US11669305
申请日：2007-01-31
申请人： Michael A. Kost
发明人： Michael A. Kost
IPC分类号： H03M1/12
CPC分类号： H03F3/217 , H03F2200/03 , H03F2200/351 , H03M3/37 , H03M3/506
摘要： Systems and methods for minimizing delay in a feedback path. In one embodiment, an analog-to-digital feedback path includes an analog-to-digital converter (ADC) configured to receive and digitize an analog signal such as an amplifier output to produce a serial digital output. A serial interface receives and parallelizes the serial digital output to produce a parallel data words that are provided to a processing unit such as a decimator. The processing unit processes the data words to produce a digital feedback signal which can then be used to modify an input signal, such as a digital audio input to the amplifier. A delay minimization subsystem is implemented in the feedback path to monitor a delay between generation of parallel data words by the serial interface and consumption of the parallel data words by the first processing unit. The delay minimization mechanism may be implemented in multiple channels of the feedback path.
摘要翻译：用于最小化反馈路径延迟的系统和方法。在一个实施例中，模数 - 数字反馈路径包括被配置为接收和数字化模拟信号（例如放大器输出）以产生串行数字输出的模拟 - 数字转换器（ADC）。串行接口接收和并行串行数字输出，以产生提供给诸如抽取器之类的处理单元的并行数据字。处理单元处理数据字以产生数字反馈信号，该数字反馈信号然后可用于修改输入信号，例如输入到放大器的数字音频。在反馈路径中实现延迟最小化子系统，以监视由串行接口产生并行数据字之间的延迟和第一处理单元对并行数据字的消耗。延迟最小化机制可以在反馈路径的多个通道中实现。

63. 发明授权

US07259618B2 Systems and methods for load detection and correction in a digital amplifier 有权
标题翻译：数字放大器负载检测和校正的系统和方法
公开(公告)号：US07259618B2
公开(公告)日：2007-08-21
申请号：US11211765
申请日：2005-08-25
申请人： Larry E. Hand , Wilson E. Taylor
发明人： Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38 , H03F1/52 , G01R19/00
CPC分类号： H03F3/2173 , H03F1/523 , H03F3/2175 , H03F2200/331 , H03F2200/426
摘要： Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.
摘要翻译：用于检测耦合到数字放大器的输出负载的阻抗并补偿放大器的响应的变化的系统和方法。本发明的一个实施例在D类脉宽调制（PWM）放大器中实现。在本实施例中，产生数字PCM测试信号。该测试信号由放大器处理以产生用于驱动扬声器的对应的模拟音频输出信号。使用与扬声器串联放置的检测电阻器来产生与参考电压相比较的测试电压。当测试电压达到参考电压时，通过检测电阻器（因此扬声器）的电流处于已知电平，因此记录数字测试信号的值。然后从测试信号值和扬声器电流确定扬声器的阻抗。

64. 发明授权

US08224469B2 Systems and methods for controlling audio volume in the processor of a high definition audio codec 失效
标题翻译：用于控制高分辨率音频编解码器处理器中音频音量的系统和方法
公开(公告)号：US08224469B2
公开(公告)日：2012-07-17
申请号：US12202355
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F17/00 , G06F9/30 , G06F9/40 , H03G3/00
CPC分类号： H03G3/3089 , G06F3/16 , G10L15/26 , G11B20/10527 , G11B2020/10574 , H03F3/217
摘要： Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.
摘要翻译：用于控制具有诸如DSP的可编程处理器的HDA编解码器中的音频信号的音频音量的系统和方法，其中编解码器通过HDA总线接收数字音频信号和音频音量控制动词，以及与音频音量控制动词由处理器在生成脉宽调制（PWM）输出信号中使用，从而控制输出信号的音频音量。除了根据音频音量水平调整音频音量之外，处理器可以被配置为调整诸如PWM死时间之类的非体积参数。编解码器可以在实现包括HDA总线和HDA编解码器的HDA系统的PC或其他系统中实现。

65. 发明申请

US20110305354A1 SYSTEMS AND METHODS FOR CONTROLLING HDA SYSTEM CAPABILITIES 有权
标题翻译：用于控制HDA系统能力的系统和方法
公开(公告)号：US20110305354A1
公开(公告)日：2011-12-15
申请号：US13218305
申请日：2011-08-25
申请人： Wilson E. Taylor , Douglas D. Gephardt , Larry E. Hand , Richard V. Spina
发明人： Wilson E. Taylor , Douglas D. Gephardt , Larry E. Hand , Richard V. Spina
IPC分类号： H03F99/00
CPC分类号： G06F3/162 , G06F21/84
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译：用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是如果可选组件连接，则不连接或将其自身配置为不同的替代配置。在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。因此，该系统可以使用相同的硬件来提供不同的特征和功能。

66. 发明授权

US08028101B2 Systems and methods for controlling HDA system capabilities 有权
标题翻译：用于控制HDA系统功能的系统和方法
公开(公告)号：US08028101B2
公开(公告)日：2011-09-27
申请号：US12202361
申请日：2008-09-01
申请人： Wilson E. Taylor , Douglas D. Gephardt , Larry E. Hand , Richard Spina
发明人： Wilson E. Taylor , Douglas D. Gephardt , Larry E. Hand , Richard Spina
IPC分类号： G06F3/00
CPC分类号： G06F3/162 , G06F21/84
摘要： Systems and methods for controlling the capabilities of an High Definition Audio (HDA) system, wherein the system determines whether an optional component such as a plug-in card is connected to the system and then configures itself in a baseline configuration if the optional component is not connected or configures itself in a different, alternative configuration if the optional component is connected. In one embodiment, a codec of the system includes a programmable processor configured to read configuration authorization information and also read configuration information from the optional component if it is connected to the system. The processor also controls the configuration of the HDA system and the operation of the codec based on the authorization and configuration information. The system can thereby provide different features and functionality using the same hardware.
摘要翻译：用于控制高清晰度音频（HDA）系统的能力的系统和方法，其中系统确定诸如插件卡的可选组件是否连接到系统，然后如果可选组件是如果可选组件连接，则不连接或将其自身配置为不同的替代配置。在一个实施例中，系统的编解码器包括可编程处理器，其被配置为读取配置授权信息，并且如果连接到系统则从可选组件读取配置信息。处理器还根据授权和配置信息控制HDA系统的配置和编解码器的操作。因此，该系统可以使用相同的硬件来提供不同的特征和功能。

67. 发明授权

US07929718B1 Systems and methods for switching and mixing signals in a multi-channel amplifier 有权
标题翻译：用于在多通道放大器中切换和混合信号的系统和方法
公开(公告)号：US07929718B1
公开(公告)日：2011-04-19
申请号：US10843852
申请日：2004-05-12
申请人： Douglas D. Gephardt , Jack B. Andersen , Larry E. Hand
发明人： Douglas D. Gephardt , Jack B. Andersen , Larry E. Hand
IPC分类号： H03F99/00 , H02B1/00 , H04R29/00 , G06F17/00
CPC分类号： H03F3/68 , H03F3/217
摘要： Systems and methods for scaling the number of output channels that can be provided in an audio amplification system. In one embodiment, a digital pulse width modulation (PWM) amplification system includes multiple four-channel PWM controller chips that are interconnected to enable synchronization and transfer of digital audio data from one chip to another. Input audio signals received by each of the channels are processed by sample rate converters to generate internal audio signals that have a predetermined sample rate and format. Each of the channels is synchronized so that the internal audio signal of each channel can be processed and output by any of the other channels. The PWM controller chips are connected by a high-speed interconnect that enables the transfer of data between them. Each input audio signal can be mapped to any of the outputs and can be mixed with other input signals.
摘要翻译：用于缩放可在音频放大系统中提供的输出通道数量的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大系统包括互连的多个四通道PWM控制器芯片，以实现数字音频数据从一个芯片到另一个芯片的同步和传输。由每个通道接收的输入音频信号由采样率转换器处理以产生具有预定采样率和格式的内部音频信号。每个通道被同步，使得每个通道的内部音频信号可以被任何其他通道处理和输出。 PWM控制器芯片通过高速互连连接，可以在它们之间传输数据。每个输入音频信号可以映射到任何一个输出，并且可以与其他输入信号混合。

68. 发明申请

US20100284547A1 SYSTEMS AND METHODS TO MINIMIZE STARTUP TRANSIENTS IN CLASS-D AMPLIFIERS 有权
标题翻译：最小化D类放大器启动瞬态的系统和方法
公开(公告)号：US20100284547A1
公开(公告)日：2010-11-11
申请号：US12839635
申请日：2010-07-20
申请人： Michael A. Kost
发明人： Michael A. Kost
IPC分类号： H04B15/00
CPC分类号： H03K7/08 , H03F1/305 , H03F3/2171 , H03K5/1515
摘要： Systems and methods for minimizing startup transients in digital audio controllers that may result in audible artifacts in the output of an audio amplification system. One embodiment comprises a digital PWM amplifier that includes a mechanism for controlling the amount of dead time in the audio output signal. When the amplifier starts up, the PWM signals provided to the output stage are simultaneously deasserted (i.e., there is dead time) for most of each switch period. The amount of dead time is gradually reduced over a series of switch periods until a nominal operating amount of dead time in each switch period is reached. Thus, the PWM signals are slowly ramped up from having a very large percentage of dead time (e.g., nearly 100%) to having a very small percentage of dead time (e.g., 1-2% to prevent shoot-through.)
摘要翻译：用于最小化数字音频控制器中的启动瞬变的系统和方法，其可能导致音频放大系统的输出中的可听见的伪影。一个实施例包括数字PWM放大器，其包括用于控制音频输出信号中的死区时间量的机构。当放大器启动时，提供给输出级的PWM信号在每个开关周期的大部分时间同时被断言（即，存在死区时间）。在一系列开关周期内死区时间逐渐减少，直到达到每个开关周期内的死区时间的标称操作量。因此，PWM信号从死区时间的很大百分比（例如近100％）缓慢上升到具有非常小百分比的死区时间（例如，1-2％以防止直通）。

69. 发明授权

US07812666B2 Low delay corrector 有权
标题翻译：低延迟校正器
公开(公告)号：US07812666B2
公开(公告)日：2010-10-12
申请号：US12542634
申请日：2009-08-17
申请人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
发明人： Daniel L. W. Chieng , Peter G. Craven , Michael A. Kost , Jack B. Andersen , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/68
CPC分类号： H03F3/217
摘要： A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.
摘要翻译：低延迟校正器（LDC）单元包括非线性函数发生器和滤波器。非线性函数发生器接收第一信号并根据第一信号和非线性函数发生器的传递函数输出第二信号。滤波器根据由非线性函数发生器输出的第二信号进给。根据提供给LDC单元的输入的输入信号和滤波器的输出，导出由非线性函数发生器接收到的第一信号。根据由非线性函数发生器接收到的第一信号和由非线性函数发生器输出的第二信号，导出LDC单元的输出。

70. 发明授权

US07728658B2 Low-noise, low-distortion digital PWM amplifier 有权
标题翻译：低噪声，低失真的数字PWM放大器
公开(公告)号：US07728658B2
公开(公告)日：2010-06-01
申请号：US11782702
申请日：2007-07-25
申请人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
发明人： Jack B. Andersen , Peter G. Craven , Michael A. Kost , Daniel L. W. Chieng , Larry E. Hand , Wilson E. Taylor
IPC分类号： H03F3/38 , H03F1/30
CPC分类号： H03F1/3258 , H03F1/26 , H03F1/3241 , H03F3/217
摘要： Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.
摘要翻译：使用低通滤波技术降低噪声和失真的数字开关放大器性能改进的系统和方法。在一个实施例中，数字脉宽调制（PWM）放大器包括被配置为接收和处理输入音频信号的信号处理设备。放大器还包括一个低通滤波器，用于滤除工厂输出的音频信号。工厂的滤波输出作为反馈被添加到输入音频信号。该设备可以由调制器和电源开关，噪声整形器或任何其它类型的设备组成。可以提供模数转换器（ADC）以将输出音频信号转换为数字信号。可以在ADC之前或之后实现滤波，如果ADC是过采样ADC，则可以在ADC之后放置抽取器。

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