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61. 发明授权

US6064593A Semiconductor integrated circuit device having an electrically erasable and programmable nonvolatile memory and a built-in processing unit 有权
标题翻译：具有电可擦除可编程非易失性存储器和内置处理单元的半导体集成电路器件
公开(公告)号：US6064593A
公开(公告)日：2000-05-16
申请号：US144194
申请日：1998-08-31
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G06F9/445 , G06F15/78 , G11C7/10 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11526 , G06F15/7814 , G06F15/7821 , G06F9/445 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C7/1045 , H01L27/115 , H01L27/11531 , H01L27/11546 , H01L27/105 , Y02B60/185
摘要： A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
摘要翻译：具有和电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储单元的可重写非易失性存储器，并且被设置为便于闪速擦除以及多个存储器单元的各个单元的选择性擦除。用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

62. 发明授权

US5900008A Semiconductor integrated circuit device 失效
公开(公告)号：US5900008A
公开(公告)日：1999-05-04
申请号：US769188
申请日：1996-12-18
申请人： Yasushi Akao , Kenichi Kuroda
发明人： Yasushi Akao , Kenichi Kuroda
IPC分类号： G06F12/06 , G06F15/78 , G06F13/00
CPC分类号： G06F15/7814
摘要： A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

63. 发明授权

US5622567A Thin film forming apparatus using laser 失效
标题翻译：使用激光的薄膜成形装置
公开(公告)号：US5622567A
公开(公告)日：1997-04-22
申请号：US158844
申请日：1993-11-29
申请人： Kazuyoshi Kojima , Tetsuya Takami , Kenichi Kuroda , Toshiyuki Oishi , Yukihiko Wada , Akihiko Furukawa
发明人： Kazuyoshi Kojima , Tetsuya Takami , Kenichi Kuroda , Toshiyuki Oishi , Yukihiko Wada , Akihiko Furukawa
IPC分类号： C23C14/02 , C23C14/08 , C23C14/22 , C23C14/28 , C23C14/34 , C23C14/54 , C23C14/56 , C23C14/00
CPC分类号： C23C14/087 , C23C14/022 , C23C14/22 , C23C14/28 , C23C14/3471 , C23C14/54 , C23C14/541 , C23C14/547 , C23C14/564 , Y10S505/732
摘要： A thin film forming apparatus using laser includes a chamber (1), a target (5) placed therein, a laser light source (10) for emitting laser beam to target (5), and a substrate holder (3). When target (5) is irradiated with laser beam (16), a plume (15) is generated, and materials included in plume (15) are deposited on the surface of a substrate (2) held by substrate holder (3). The laser beam emitted from laser light source (10) has its cross section shaped to a desired shape when passed through a shielding plate (4804), for example, so that the surface of the target (5) is irradiated with the beam having uniform light intensity distribution. Therefore, a plume (15) having uniform density distribution of active particles is generated, and therefore a thin film of high quality can be formed over a wide area with uniform film quality, without damaging the substrate.
摘要翻译：使用激光的薄膜形成装置包括：室（1），放置在其中的靶（5），用于将目标物（5）发射激光的激光源（10）和基板保持器（3）。当用激光束（16）照射靶（5）时，产生羽流（15），并且包含在羽流（15）中的材料沉积在由基板保持器（3）保持的基板（2）的表面上。从激光光源（10）发射的激光束的横截面通过遮蔽板（4804）时成形为期望的形状，使得靶（5）的表面被均匀地照射光强分布。因此，产生具有均匀的活性粒子密度分布的羽流（15），因此可以在不损害基板的情况下，在宽的区域上形成具有均匀膜质量的高质量的薄膜。

64. 发明授权

US5548146A Nonvolatile memory device having source and drain of memory cells integrally formed with data-source lines 失效
标题翻译：具有与数据源线一体形成的存储单元的源极和漏极的非易失性存储器件
公开(公告)号：US5548146A
公开(公告)日：1996-08-20
申请号：US470008
申请日：1995-06-06
申请人： Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
发明人： Kenichi Kuroda , Kazuyoshi Shiba , Akinori Matsuo
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/7883
摘要： A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulatedly above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding, necessary high voltages can be generated by the internal circuits.
摘要翻译：第一导电类型的半导体衬底在其主表面上通过第一栅极绝缘膜形成浮栅，并且还通过第二栅极绝缘膜在浮栅上形成控制栅极。在成对的源极和漏极中的一个中，在衬底的主表面上绝缘地设置浮置栅极，形成具有比成对的源极和漏极的杂质浓度低的第二导电类型的半导体区域衬底的一部分与浮动栅极重叠。如此构造的非易失性存储器件的写入操作是通过将电子从浮栅提取到具有具有较高杂质浓度的第二导电类型的半导体区域的成对源极和漏极中的另一个，通过电子的FN隧穿流过第一栅极绝缘膜及其擦除操作，其通过由穿过第一栅极绝缘膜的电子的FN隧穿而从成对的源极和漏极或半导体衬底注入到浮置栅极中进行。数据线或源极线可以在字线方向上彼此相邻的存储单元之间共享，使得存储器单元可以基本上小型化。可以通过隧道电流进行写入操作和擦除操作，使得内部电路可以产生相应的必要的高电压。

65. 发明授权

US5524093A Semiconductor memory device having an arrangement to reduce stresses on non-selected ferroelectric capacitors while achieving high integration 失效
标题翻译：半导体存储器件具有减少未选择的铁电电容器的应力同时实现高集成度的装置
公开(公告)号：US5524093A
公开(公告)日：1996-06-04
申请号：US394248
申请日：1995-02-24
申请人： Kenichi Kuroda
发明人： Kenichi Kuroda
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22
摘要： A high integration semiconductor memory device which can reduce stresses placed on non-selected ferroelectric capacitors. A plurality of subblock memory circuits are provided wherein first electrodes forming a plurality of ferroelectric capacitors are respectively provided at first address selection switches, a plurality of other electrodes arranged side by side in the horizontal direction are provided so as to meet at right angles to the first electrodes, and the plurality of ferroelectric capacitors are formed at points where the first electrodes and the other electrodes respectively intersect. Different addresses are respectively assigned to the first address selection lines of the respective subblock memory circuits and common addresses are respectively assigned to the second address selection lines of the plurality of subblock memory circuits, thereby forming a shared address selection circuit. The first address selection line, first switching elements and one second address selection line can be used to develop polarization in the ferroelectric capacitors. Further, the remaining second address selection lines are supplied with such a non-selected potential that a voltage applied to the ferroelectric capacitors reaches substantially half the voltage applied to the selected ferroelectric capacitor. On the other hand, when the first address selection line is brought into a non-selected state and the first switching elements are brought into an OFF state, the plurality of second address selection lines are supplied with such a non-selected potential that the voltage applied to the ferroelectric capacitors reach zero.
摘要翻译：一种高集成半导体存储器件，其可以降低施加在非选择的铁电电容器上的应力。提供了多个子块存储器电路，其中在第一地址选择开关处分别设置形成多个铁电电容器的第一电极，在水平方向上并排布置的多个其它电极被设置为与第一电极和多个铁电电容器形成在第一电极和其他电极分别相交的点处。不同的地址被分配给各个子块存储器电路的第一地址选择线，并且公共地址分别被分配给多个子块存储器电路中的第二地址选择线，从而形成共享地址选择电路。第一地址选择线，第一开关元件和第二地址选择线可以用于在铁电电容器中产生极化。此外，剩余的第二地址选择线被提供有这样的非选择电位，使得施加到铁电电容器的电压达到施加到所选择的铁电电容器的电压的大致一半。另一方面，当第一地址选择线处于非选择状态并且第一开关元件处于截止状态时，多个第二地址选择线被提供有非选择电位，使得电压施加到铁电电容器达到零。

66. 发明授权

US4918501A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4918501A
公开(公告)日：1990-04-17
申请号：US291647
申请日：1988-12-29
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , Y10S257/90
摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.
摘要翻译：公开了一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和LDD结构的第二场效应晶体管作为除了存储单元之外的元件，并且被用作EPROM。作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度。

67. 发明授权

US4784968A Process for manufacturing a semiconductor device having MIS-type field effect transistors with impurity region below the gate electrode 失效
标题翻译：具有MIS栅型电极下方杂质区域的MIS型场效应晶体管的半导体器件的制造方法
公开(公告)号：US4784968A
公开(公告)日：1988-11-15
申请号：US75411
申请日：1987-07-20
申请人： Kazuhiro Komori , Kenichi Kuroda , Kousuke Okuyama
发明人： Kazuhiro Komori , Kenichi Kuroda , Kousuke Okuyama
IPC分类号： H01L29/10 , H01L29/78 , H01L21/265 , B01J17/00
CPC分类号： H01L29/1083 , H01L29/1033 , H01L29/78 , Y10S438/919
摘要： Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.
摘要翻译：这里公开了一种MOS型场效应晶体管，其中在沟道下方形成具有与衬底相同类型的导电性并且杂质浓度高于衬底的半导体区域，以使其两端处于接触状态与源极和漏极区域。半导体区域限制耗尽层从源极和漏极区域的延伸，并限制短沟道效应。在半导体区域和源极和漏极区域之间的结电容小。

68. 发明授权

US3987377A Elastic surface wave propagation device 失效
标题翻译：弹性表面波传播装置
公开(公告)号：US3987377A
公开(公告)日：1976-10-19
申请号：US547210
申请日：1975-02-05
申请人： Kenichi Kuroda , Fujio Ishihara
发明人： Kenichi Kuroda , Fujio Ishihara
IPC分类号： H03H9/25 , H03H3/08 , H03H9/00 , H03H9/02 , H03H9/30 , H03H9/42 , H04R17/00 , H03H9/26 , H01L41/18 , H03H9/32
CPC分类号： H03H9/02551 , H03H9/02818 , H03H9/42
摘要： An elastic surface wave propagation device is disclosed which is composed of a substrate for elastic surface wave propagation and at least one transducer disposed on the major surface of the substrate for converting an electric signal into an elastic surface wave or vice versa. The substrate is formed of quartz crystal and the major surface of the substrate is 43.degree. rotated Y cut plane of the quartz crystal. The angle between the direction of propagation of the elastic surface wave and the X-axis direction of the quartz crystal is selected to be in the range of 8.degree. to 12.degree. so that spurious components are sufficiently suppressed or negligible.
摘要翻译：公开了一种弹性表面波传播装置，其由用于弹性表面波传播的基板和设置在基板的主表面上的至少一个换能器将电信号转换成弹性表面波，或反之亦然。基板由石英晶体形成，基板的主表面为石英晶体的43°旋转Y切割面。弹性表面波的传播方向与石英晶体的X轴方向之间的角度选择在8°至12°的范围内，使得杂散成分被充分抑制或可忽略。

69. 发明授权

US08765168B2 Compositions of a fluorapatite and methods of use 有权
标题翻译：氟磷灰石的组成和使用方法
公开(公告)号：US08765168B2
公开(公告)日：2014-07-01
申请号：US13505487
申请日：2010-11-08
申请人： Brian H. Clarkson , Kenichi Kuroda
发明人： Brian H. Clarkson , Kenichi Kuroda
IPC分类号： A61F13/02
CPC分类号： A61K33/42 , A61K6/0017 , A61K6/0038 , A61K6/033 , A61K6/083 , A61K8/19 , A61K8/24 , A61K8/8152 , A61K9/0063 , A61Q11/00 , C08L33/00
摘要： Compositions of fluorapatite derivative crystals are disclosed herein. Also disclosed are methods of using these compositions to treat tooth sensitivity, to use as an anticaries treatment, to use as a restorative material, to use as a tooth surface whitener, and to combat or lessen the side effects of tooth whitening.
摘要翻译：本文公开了氟磷灰石衍生物晶体的组成。还公开了使用这些组合物来治疗牙齿敏感性，用作防龋处理，用作修复材料，用作牙齿表面增白剂以及抵抗或减轻牙齿美白的副作用的方法。

70. 发明授权

US08426969B2 Semiconductor device having active region and dummy wirings 有权
标题翻译：具有有源区和虚拟布线的半导体器件
公开(公告)号：US08426969B2
公开(公告)日：2013-04-23
申请号：US13362385
申请日：2012-01-31
申请人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
发明人： Kenichi Kuroda , Kozo Watanabe , Hirohiko Yamamoto
IPC分类号： H01L23/48
CPC分类号： H01L23/5283 , H01L21/31053 , H01L21/74 , H01L21/76224 , H01L21/76229 , H01L23/522 , H01L23/528 , H01L23/53228 , H01L27/0207 , H01L27/11807 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/4925 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
摘要翻译：提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案，在虚拟区域FA中。由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

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