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61. 发明授权

US08642400B2 Method of manufacturing semiconductor device including capacitor element 有权
标题翻译：制造包括电容器元件的半导体器件的方法
公开(公告)号：US08642400B2
公开(公告)日：2014-02-04
申请号：US13434177
申请日：2012-03-29
申请人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
发明人： Tetsuo Yoshimura , Kenichi Watanabe , Satoshi Otsuka
IPC分类号： H01L21/20
CPC分类号： H01G4/005 , H01G4/228 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes: forming a first metal film on an insulating film over a substrate; forming a capacitor lower electrode by patterning the first metal film; and forming a dielectric film on upper and side surfaces of the capacitor lower electrode and on the insulating film. The method further includes: forming a conductive protection film on the dielectric film; patterning the conductive protection film into a shape of covering the capacitor lower electrode; forming a capacitor dielectric film in a shape of covering the upper and side surfaces of the capacitor lower electrode, by patterning the dielectric film so that the patterned conductive protection film covers an upper surface of the capacitor dielectric film; forming a second metal film on the patterned conductive protection film; and forming a capacitor upper electrode that covers at least an upper surface of the patterned conductive protection film.
摘要翻译：一种制造半导体器件的方法包括：在衬底上的绝缘膜上形成第一金属膜; 通过图案化第一金属膜形成电容器下电极; 并且在电容器下电极的上表面和侧表面上以及绝缘膜上形成电介质膜。该方法还包括：在电介质膜上形成导电保护膜; 将导电保护膜图案化成覆盖电容器下电极的形状; 通过对所述电介质膜进行构图来形成覆盖所述电容器下电极的上表面和所述侧表面的电容器电介质膜，使得所述图案化的导电保护膜覆盖所述电容器电介质膜的上表面; 在图案化的导电保护膜上形成第二金属膜; 以及形成覆盖图案化的导电保护膜的至少上表面的电容器上电极。

62. 发明授权

US08633595B2 Semiconductor device having groove-shaped via-hole 有权
公开(公告)号：US08633595B2
公开(公告)日：2014-01-21
申请号：US13548966
申请日：2012-07-13
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L23/522 , H01L29/74 , H01L27/108 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/76804 , H01L21/76843 , H01L23/481 , H01L23/485 , H01L23/522 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/5283 , H01L23/53204 , H01L23/53223 , H01L23/53228 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L23/562 , H01L23/58 , H01L23/585 , H01L29/0607 , H01L29/0611 , H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

63. 发明申请

US20130333200A1 SLIDING MEMBER MANUFACTURING METHOD 审中-公开
标题翻译：滑动构件制造方法
公开(公告)号：US20130333200A1
公开(公告)日：2013-12-19
申请号：US14002655
申请日：2012-02-22
申请人： Yoshitomo Ishizaki , Kenichi Watanabe , Naoya Masahashi
发明人： Yoshitomo Ishizaki , Kenichi Watanabe , Naoya Masahashi
IPC分类号： B23P15/00
CPC分类号： B23P15/00 , B22F3/105 , B22F3/14 , B22F5/00 , B22F5/008 , B22F7/02 , B22F7/08 , B23K10/027 , B23K35/007 , B23K2103/22 , B32B15/015 , C22C1/02 , C22C1/0425 , C22C9/01 , C22C9/02 , C22C9/04 , C22C9/06 , C22C9/08 , C22C38/02 , C22C38/04 , C22C38/18 , C22C38/22 , C22C38/40 , F04B1/0408 , F04B1/124 , F04B1/2078 , F04B53/14 , F05C2201/0475 , Y10T29/49
摘要： A sliding member manufacturing method for manufacturing a sliding member having a sliding portion, wherein the sliding member is manufactured by forming a solid phase joint between a bulk material that is made of an iron based metal and functions as a main body portion of the sliding member and a bulk material that is made of a Cu alloy and functions as the sliding portion by applying heat and pressure thereto using a spark plasma sintering method.
摘要翻译：一种用于制造具有滑动部分的滑动构件的滑动构件制造方法，其中，滑动构件通过在由铁基金属制成并且用作滑动构件的主体部分的体材料之间形成固相接头以及由Cu合金制成并通过使用放电等离子体烧结方法向其施加热和压力而用作滑动部分的散装材料。

64. 发明授权

US08592884B2 Semiconductor device including capacitor 有权
标题翻译：半导体器件包括电容器
公开(公告)号：US08592884B2
公开(公告)日：2013-11-26
申请号：US13426014
申请日：2012-03-21
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L27/108
CPC分类号： H01L21/486 , H01L23/5223 , H01L23/5226 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.
摘要翻译：基板在第一布线层111上设置有第一布线层111，层间绝缘膜132，形成在层间绝缘膜中的孔112A，覆盖孔112A的第一金属层112，形成在第一布线层111上的第二金属层113 孔112A，第一金属层112上的介电绝缘膜135和介电绝缘膜135上的第二布线层114-116，其中第一金属层112构成下电极的至少一部分，面向第二布线层114-116的下电极构成上电极，电容器160由下电极，电介质绝缘膜135和上电极P1构成。

65. 发明授权

US08562041B2 Bumper structure 有权
标题翻译：保险杠结构
公开(公告)号：US08562041B2
公开(公告)日：2013-10-22
申请号：US13318489
申请日：2010-05-13
申请人： Masao Kinefuchi , Tomokazu Nakagawa , Takunori Yamaguchi , Mie Tachibana , Kenichi Watanabe
发明人： Masao Kinefuchi , Tomokazu Nakagawa , Takunori Yamaguchi , Mie Tachibana , Kenichi Watanabe
IPC分类号： B60R19/04
CPC分类号： B60R19/18 , B60R19/03 , B60R19/12 , B60R2019/1806 , B60R2019/1833 , Y10T292/0925
摘要： A bumper structure which as a whole has a reduced weight and which has sufficient buckling strength. A bumper structure has a box-like outer shape constituted of a front flange (2), a rear flange (3), an upper web (4), and a lower web (5) which consist of a steel material. An intermediate web (6) consisting of a material other than the steel material is disposed between the upper web (4) and the lower web (5). If the Young's modulus of the steel material is E1, the density of the steel material is ρ1, the Young's modulus of the material which forms the intermediate web (6) is E2, and the density of the material which forms the intermediate web (6) is ρ2, the bumper structure satisfies E1/ρ13
摘要翻译：保险杠结构整体上具有减轻的重量并具有足够的弯曲强度。保险杠结构具有由钢材构成的前凸缘（2），后凸缘（3），上腹板（4）和下腹板（5）构成的箱状外形。由上述纤维网（4）和下部纤维网（5）之间设置由钢材以外的材料构成的中间纤维网（6）。如果钢材的杨氏模量为E1，则钢材的密度为rho1，形成中间纤维网（6）的材料的杨氏模量为E2，形成中间纤维网（6）的材料的密度）为rho2，保险杠结构满足E1 / rho13

66. 发明授权

US08507377B2 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
标题翻译：半导体装置及其制造方法以及相移掩模
公开(公告)号：US08507377B2
公开(公告)日：2013-08-13
申请号：US12764210
申请日：2010-04-21
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： H01L21/4763
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.
摘要翻译：一种制造半导体器件的方法，包括形成有集成电路的集成电路部分和包括围绕所述集成电路部分的金属膜的主壁部分的步骤包括以下步骤：在集成电路部分之间选择性地形成包括金属膜的副壁部分电路部分和主壁部分，并联形成集成电路部分和主壁部分。在主壁部的每个角部和所得到的半导体器件的集成电路部分之间设置有“L”形的副壁部。

67. 发明授权

US08264064B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08264064B2
公开(公告)日：2012-09-11
申请号：US12702729
申请日：2010-02-09
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.
摘要翻译：半导体器件包括半导体衬底，其中在内部电路在中心位置形成在半导体衬底上形成的绝缘层，以及由嵌入绝缘层中的金属插塞形成的防潮环，围绕所述内部电路，所述防湿环形成为在所述半导体基板上延伸的形状，所述防湿环包括与所述半导体基板的表面平行的第一方向上直线延伸的第一延伸部，第一延伸部分，其在与第一延伸部分正交的第二方向上延伸;以及第二延伸部分，其垂直于垂直部分并平行于半导体基板的表面，第二延伸部分与第一延伸部分间隔开，第二延伸部分横穿垂直部分的部分。

68. 发明授权

US08264062B2 Semiconductor device having capacitor capable of reducing additional processes and its manufacture method 有权
标题翻译：具有能够减少附加工艺的电容器的半导体器件及其制造方法
公开(公告)号：US08264062B2
公开(公告)日：2012-09-11
申请号：US11505945
申请日：2006-08-18
申请人： Kenichi Watanabe
发明人： Kenichi Watanabe
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/00
CPC分类号： H01L23/5223 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.
摘要翻译：通过层间绝缘膜形成第一电容器凹部和布线沟槽。下部电极填充第一电容器凹部，并且第一布线填充布线沟槽。蚀刻停止膜和通孔层绝缘膜设置在层间绝缘膜上。第一通孔延伸穿过通孔层绝缘膜和蚀刻阻挡膜并到达第一布线，并且第一插头填充第一通孔。通过通孔层绝缘膜形成第二电容器凹部，第二电容器凹部至少部分地与下电极重叠，如图所示。上电极覆盖第二电容器凹部的底表面和侧表面。电容器由上电极，蚀刻停止膜和下电极构成。连接到第一插头的第二连接件形成在通孔层绝缘膜上。

69. 发明授权

US08207610B2 Semiconductor device having a multilayer interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08207610B2
公开(公告)日：2012-06-26
申请号：US11868102
申请日：2007-11-14
申请人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
发明人： Kenichi Watanabe , Tomoji Nakamura , Satoshi Otsuka
IPC分类号： H01L29/40
CPC分类号： H01L23/481 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure device having a multilayer interconnection structure; such a structure includes at least a first interconnection layer and a second interconnection layer; the first interconnection layer includes a first conductor pattern embedded in a first interlayer insulation film and a second conductor pattern embedded in said first interlayer insulation film; the second interconnection layer includes a third conductor pattern embedded in a second interlayer insulation film; the third conductor pattern being coupled to an extension part in a part thereof so as to extend in said second interlayer insulation film in a plane of said second interlayer insulation film; the extension part of said third conductor pattern, said first via-plug and said second viaplug forming help form a dual damascene structure.
摘要翻译：一种具有多层互连结构的结构装置; 这种结构至少包括第一互连层和第二互连层; 第一互连层包括嵌入在第一层间绝缘膜中的第一导体图案和嵌入所述第一层间绝缘膜中的第二导体图案; 第二互连层包括嵌入第二层间绝缘膜中的第三导体图案; 所述第三导体图案在其一部分中被连接到延伸部分，以在所述第二层间绝缘膜中在所述第二层间绝缘膜的平面中延伸; 所述第三导体图案的延伸部分，所述第一通孔插头和所述第二插销形成帮助形成双镶嵌结构。

70. 发明授权

US08042280B2 Lens shape measurement device 有权
标题翻译：镜片形状测量装置
公开(公告)号：US08042280B2
公开(公告)日：2011-10-25
申请号：US12809183
申请日：2008-12-18
申请人： Takahiro Watanabe , Kenichi Watanabe , Kenji Miyashita , Masahiro Jinbo
发明人： Takahiro Watanabe , Kenichi Watanabe , Kenji Miyashita , Masahiro Jinbo
IPC分类号： G01B1/00
CPC分类号： G01B5/213 , B24B9/148
摘要： An arithmetic control circuit (52) is configured to bring the measuring element (38) for a lens into contact with at least two points (measurement points P1, P2) of one of two refracting surfaces of the lens Lm held in the lens holder by controlling the measuring element shifter (driving motor 6), obtain the coordinates of the two points according to the detection signal from the position detector (linear scales 24, 40), and obtain a curve value Cv of one refracting surface of the lens from the difference of the coordinates of the two points.
摘要翻译：运算控制电路（52）被配置为使透镜的测量元件（38）与保持在透镜夹持器中的透镜Lm的两个折射表面的两个折射表面中的至少两个点（测量点P1，P2）接触，控制测量元件移位器（驱动电动机6），根据来自位置检测器（线性标尺24,40）的检测信号获得两点的坐标，并从透镜的一个折射表面获得一个折射表面的曲线值Cv 两点的坐标差。

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