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61. 发明授权

US4905314A Semiconductor integrated circuit device having an object circuit to which output voltages of the sub- and main booster circuits are applied 失效
标题翻译：半导体集成电路装置具有对主电路施加副主电路和主升压电路的输出电压的目标电路
公开(公告)号：US4905314A
公开(公告)日：1990-02-27
申请号：US184580
申请日：1988-04-21
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
CPC分类号： G11C5/145 , G11C16/30 , H03K17/06 , H03K3/356008
摘要： A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.

62. 发明授权

US4804929A Control pulse generator 失效
标题翻译：控制脉冲发生器
公开(公告)号：US4804929A
公开(公告)日：1989-02-14
申请号：US101667
申请日：1987-09-28
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： H03K3/037 , H03K17/22 , H03L1/00 , H03B1/00
CPC分类号： H03K17/223
摘要： A control pulse generator according to the present invention includes a voltage generator for generating an output voltage proportional to a power supply voltage, an inverter for generating an inversion signal whose signal level is inverted when the output voltage from the voltage generator reaches a predetermined value, and a pulse signal generator for delaying a level inversion timing of the inversion signal by a predetermined delay time, and generating a control pulse having a width corresponding to the delay time. According to the control pulse generator with the above arrangement, the width of the control pulse can be determined on the basis of the delay time of the pulse signal generator, regardless of rise states of the power supply voltage. In addition, the height of the control pulse can be set at a desired value according to a supply voltage to the pulse signal generator, regardless of rise states of the supply voltage.
摘要翻译：根据本发明的控制脉冲发生器包括用于产生与电源电压成比例的输出电压的电压发生器，用于产生当来自电压发生器的输出电压达到预定值时信号电平反转的反相信号的反相器，以及脉冲信号发生器，用于将反转信号的电平反转定时延迟预定的延迟时间，并产生具有对应于延迟时间的宽度的控制脉冲。根据具有上述配置的控制脉冲发生器，无论电源电压的上升状态如何，可以基于脉冲信号发生器的延迟时间来确定控制脉冲的宽度。此外，无论电源电压的上升状态如何，控制脉冲的高度可以根据与脉冲信号发生器的电源电压设定在期望值。

63. 发明授权

US4794562A Electrically-erasable/programmable nonvolatile semiconductor memory device 失效
标题翻译：电可擦除/可编程非易失性半导体存储器件
公开(公告)号：US4794562A
公开(公告)日：1988-12-27
申请号：US94458
申请日：1987-09-09
申请人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
发明人： Hideo Kato , Hiroshi Iwahashi , Masamichi Asano , Akira Narita , Shinichi Kikuchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L29/7883 , H01L27/115
摘要： In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.
摘要翻译：在根据本发明的电可擦除/可编程非易失性半导体存储器件中，一位存储单元由选择MOS晶体管和数据存储MOS晶体管的串联电路构成。在数据存储MOS晶体管中形成浮栅电极和控制栅极，通过栅极绝缘膜在浮动栅极的一部分形成在数据存储MOS晶体管的沟道区上。浮置栅电极的另一部分通过栅极绝缘膜形成在数据存储MOS晶体管的漏极区上，栅极绝缘膜的一部分比栅极绝缘膜充分薄。浮栅电极的一个和另外部分在结构上彼此分离，但是在场区域上彼此电连接。通过栅极绝缘膜在其上形成具有与浮栅电极基本相同形状的控制栅电极。

64. 发明授权

US4557476A Cigarette case jugglery device 失效
标题翻译：香烟盒jugglery设备
公开(公告)号：US4557476A
公开(公告)日：1985-12-10
申请号：US632645
申请日：1984-07-20
申请人： Hideo Kato
发明人： Hideo Kato
IPC分类号： A63J21/00 , E05B37/20
CPC分类号： A63J21/00 , Y10T70/7169
摘要： A jugglery device using cigarettes comprises a hollow rectangular parallelpiped casing formed by parallel rectangular upper and bottom walls. A pair of side walls connect opposite side edges of the upper and bottom walls, and an end wall connects opposite end edges of the upper and bottom walls. A drawer assembly is disposed slidably in relation to the bottom wall through the open end of the casing. The drawer accommodates a plurality of cigarettes. The drawer has a bottom wall slidable on the bottom wall of the casing, a pair of side walls and an end wall to connect opposite end edges of the side walls. A first auxiliary end wall protrudes from one of the other opposite end edges of the side wall toward the other end edge. A second bottom wall is slidably disposed on the bottom wall of the drawer assembly and is of nearly the same area as the bottom wall of the drawer assembly. A pair of second auxiliary walls are vertically raised from a part of the opposite end edges, one of the second auxiliary end walls touching a part of the end wall of the drawer assembly when the drawer assembly is in its minimum sliding position in relation to the second bottom wall; while the other second auxiliary end wall forms another end wall of the drawer assembly, and the second bottom wall is selectively engageable with either the drawer assembly or the casing in the minimum sliding position of the drawer assembly with respect to said casing.
摘要翻译：使用香烟的火腿装置包括由平行的矩形上壁和底壁形成的中空矩形平行皮套。一对侧壁连接上壁和底壁的相对侧边缘，并且端壁连接上壁和底壁的相对端边缘。抽屉组件通过壳体的开口端相对于底壁可滑动地设置。抽屉容纳多根香烟。抽屉具有可在壳体的底壁上滑动的底壁，一对侧壁和用于连接侧壁的相对端边缘的端壁。第一辅助端壁从侧壁的另一个相对端边缘之一朝向另一端边缘突出。第二底壁可滑动地设置在抽屉组件的底壁上，并且与抽屉组件的底壁几乎相同的面积。一对第二辅助壁从相对端边缘的一部分垂直地升起，当抽屉组件相对于第二辅助壁处于最小滑动位置时，第二辅助端壁中的一个接触抽屉组件的端壁的一部分第二个底壁; 而另一个第二辅助端壁形成抽屉组件的另一个端壁，并且第二底壁在抽屉组件相对于所述壳体的最小滑动位置中可选择性地与抽屉组件或壳体接合。

65. 发明授权

US4198431A Alkyl N-(3-trifluoromethylphenyl)-anthranilate 失效
标题翻译： N-（3-三氟甲基苯基） - 邻氨基苯甲酸烷基酯
公开(公告)号：US4198431A
公开(公告)日：1980-04-15
申请号：US874494
申请日：1978-02-02
申请人： Hideo Kato
发明人： Hideo Kato
IPC分类号： A61K31/245 , A61K31/195 , A61K31/24 , A61P25/04 , A61P29/00 , C07C20060101 , C07C67/00 , C07C227/00 , C07C227/18 , C07C229/58 , C07C101/54
CPC分类号： A61K31/245 , C07C229/58 , Y10S514/887
摘要： N-(3-trifluoromethylphenyl)anthranilic acid esters represented by the formula (I): ##STR1## wherein R represents an alkyl group having 4 to 8 carbon atoms, are disclosed.The esters are useful as anti-inflammatory agents, particularly for an external application, with reduced toxicity. These esters are of great importance as non-steroid type anti-inflammatory agents for topical administration.
摘要翻译：公开了由式（I）表示的N-（3-三氟甲基苯基）邻氨基苯甲酸酯：其中R表示具有4至8个碳原子的烷基的式（I）。所述酯可用作抗炎剂，特别是外用的抗炎剂，毒性降低。这些酯作为用于局部给药的非类固醇型抗炎剂是非常重要的。

66. 发明授权

US4008124A Process for the isomerization of glucose into fructose 失效
标题翻译：将葡萄糖异构化为果糖的方法
公开(公告)号：US4008124A
公开(公告)日：1977-02-15
申请号：US588823
申请日：1975-06-20
申请人： Yoshimasa Fujita , Akiyoshi Matsumoto , Hachiro Ishikawa , Tadashi Hishida , Hideo Kato , Hiroshi Takamisawa
发明人： Yoshimasa Fujita , Akiyoshi Matsumoto , Hachiro Ishikawa , Tadashi Hishida , Hideo Kato , Hiroshi Takamisawa
IPC分类号： C12N9/92 , C08B37/00 , C12N9/96 , C12N11/08 , C12N11/10 , C12P19/24 , C12D13/02
CPC分类号： C08B37/0039 , C12N11/08 , C12N11/10 , C12P19/24 , Y10S435/886
摘要： There is disclosed a process for isomerization of glucose into fructose which comprises contacting an aqueous glucose solution with glucose isomerase in the presence of iron ion and magnesium ion, said glucose isomerase being in the form of insolubilized glucose isomerase adsorbed on a carrier.
摘要翻译：公开了一种将葡萄糖异构化成果糖的方法，该方法包括在铁离子和镁离子存在下使葡萄糖水溶液与葡萄糖异构酶接触，所述葡萄糖异构酶是吸附在载体上的不溶葡萄糖异构酶的形式。

67. 发明授权

US3980643A Novel piperazine- and homopiperazine-monoalkanol esters and a process of production thereof 失效
标题翻译：新型哌嗪和高哌嗪 - 单链烷醇酯及其制备方法
公开(公告)号：US3980643A
公开(公告)日：1976-09-14
申请号：US430925
申请日：1974-01-04
申请人： Hideo Kato , Takaaki Mouri , Tomoyasu Nishikawa
发明人： Hideo Kato , Takaaki Mouri , Tomoyasu Nishikawa
IPC分类号： C07D213/79 , C07D243/08 , C07D295/088 , C07D295/04
CPC分类号： C07D213/79 , C07D243/08 , C07D295/088
摘要： There is provided piperazine or homopiperazine-monoalkanol esters and salts thereof. These compounds are prepared by esterification of the corresponding alkanol compounds.The novel compounds are characterized by therapeutic activity and specifically, analgetic, coronary vaso-dilative, anti-convulsant, and blood pressure-decreasing properties.
摘要翻译：提供哌嗪或高哌嗪 - 单链烷醇酯及其盐。这些化合物通过相应的链烷醇化合物的酯化制备。

68. 发明授权

US09670593B2 Method for recharging raw material polycrystalline silicon 有权
公开(公告)号：US09670593B2
公开(公告)日：2017-06-06
申请号：US13329368
申请日：2011-12-19
申请人： Hideo Kato , Satoko Yoshimura , Takeshi Ninomiya
发明人： Hideo Kato , Satoko Yoshimura , Takeshi Ninomiya
IPC分类号： C30B15/02 , C30B29/06 , C30B11/00 , C30B15/00
CPC分类号： C30B29/06 , C30B11/001 , C30B15/002 , C30B15/02 , Y10T117/1056
摘要： A method for recharging raw material polycrystalline silicon which enables large chunks of polycrystalline silicon to be recharged to a CZ ingot growth process while preventing the CZ crucible from being damaged and restricting a decline of the dislocation free rate and the quality of the grown ingot. Polycrystalline silicon chunks are recharged by first forming cushioning layer silicon of smaller chunks. The cushioning layer of polycrystalline silicon chunks are deposited on a surface of the residual silicon melt in a crucible. Subsequently, large-sized polycrystalline silicon chunks are introduced onto the cushioning layer, the cushioning layer cushioning the impact due to dropping of the large-sized polycrystalline silicon chunks.

69. 发明申请

US20120160156A1 Method For Recharging Raw Material Polycrystalline Silicon 有权
标题翻译：多晶硅原料再充电方法
公开(公告)号：US20120160156A1
公开(公告)日：2012-06-28
申请号：US13329368
申请日：2011-12-19
申请人： Hideo Kato , Satoko Yoshimura , Takeshi Ninomiya
发明人： Hideo Kato , Satoko Yoshimura , Takeshi Ninomiya
IPC分类号： C30B15/02
CPC分类号： C30B29/06 , C30B11/001 , C30B15/002 , C30B15/02 , Y10T117/1056
摘要： A method for recharging raw material polycrystalline silicon which enables large chunks of polycrystalline silicon to be recharged to a CZ ingot growth process while preventing the CZ crucible from being damaged and restricting a decline of the dislocation free rate and the quality of the grown ingot. Polycrystalline silicon chunks are recharged by first forming cushioning layer silicon of smaller chunks. The cushioning layer of polycrystalline silicon chunks are deposited on a surface of the residual silicon melt in a crucible. Subsequently, large-sized polycrystalline silicon chunks are introduced onto the cushioning layer, the cushioning layer cushioning the impact due to dropping of the large-sized polycrystalline silicon chunks.
摘要翻译：一种用于对原料多晶硅进行再充电的方法，其能够使大块多晶硅再次充电至CZ锭生长过程，同时防止CZ坩埚被损坏并限制位错自由率和生长锭的质量的下降。通过首先形成更小块的缓冲层硅来对多晶硅块进行再充电。多晶硅块的缓冲层沉积在坩埚中的残余硅熔体的表面上。随后，将大尺寸多晶硅块引入到缓冲层上，缓冲层缓冲了由于大尺寸多晶硅块的掉落引起的冲击。

70. 发明申请

US20120160154A1 Method For Producing Silicon Single Crystal Ingot 审中-公开
标题翻译：生产硅单晶锭的方法
公开(公告)号：US20120160154A1
公开(公告)日：2012-06-28
申请号：US13329378
申请日：2011-12-19
申请人： Hideo Kato , Hideaki Murakami
发明人： Hideo Kato , Hideaki Murakami
IPC分类号： C30B15/14
CPC分类号： C30B29/06 , C30B15/00 , C30B35/007
摘要： An ingot production method which makes it possible to greatly restrict formation of pinholes or substantially prevent them avoids the use of substantial amounts of small-sized polycrystalline silicon chunks of polycrystalline silicon chunks, only middle-sized polycrystalline silicon chunks and large-sized polycrystalline silicon chunks. In the step of filling polycrystalline silicon, the polycrystalline silicon chunks are randomly supplied into the crucible.
摘要翻译：可以大大限制针孔的形成或基本防止它们的锭生产方法避免使用大量的多晶硅块的小尺寸多晶硅块，只有中等尺寸的多晶硅块和大尺寸多晶硅块。在填充多晶硅的步骤中，将多晶硅块随机提供给坩埚。

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