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61. 发明申请

US20120235244A1 Semiconductor Structure and Method for Manufacturing the Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120235244A1
公开(公告)日：2012-09-20
申请号：US13380482
申请日：2011-04-18
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/088 , H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26586 , H01L21/28518 , H01L21/823814 , H01L21/823864 , H01L29/41775 , H01L29/456 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7835
摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate, forming an active region on the substrate, forming a gate stack or a dummy gate stack on the active region, forming a source extension region and a drain extension region at opposite sides of the gate stack or dummy gate stack, forming a spacer on sidewalls of the gate stack or dummy gate stack, and forming a source and a drain on portions of the active region exposed by the spacer and the gate stack or dummy gate stack; removing at least a part of a source-side portion of the spacer, such that the source-side portion of the spacer has a thickness less than that of a drain-side portion of the spacer; and forming a contact layer on portions of the active region exposed by the spacer and the gate stack or dummy gate stack. Correspondingly, the present invention further provides a semiconductor structure. The present invention is beneficial to the reduction of the contact resistance of the source extension region and meanwhile can also reduce the parasitic capacitance between the gate and the drain extension region.
摘要翻译：一种用于制造半导体结构的方法，包括：提供衬底，在衬底上形成有源区，在有源区上形成栅叠层或虚栅极叠层，在源极延伸区和漏极延伸区的相对两侧形成栅极堆叠或伪栅极堆叠，在栅极堆叠或伪栅极堆叠的侧壁上形成间隔物，以及在由间隔物和栅极堆叠或伪栅极堆叠暴露的有源区域的部分上形成源极和漏极; 去除所述间隔物的源极侧部分的至少一部分，使得所述间隔物的源极侧部分的厚度小于所述间隔物的漏极侧部分的厚度; 以及在由间隔件和栅极堆叠或虚拟栅极堆叠暴露的有源区域的部分上形成接触层。相应地，本发明还提供一种半导体结构。本发明有益于降低源延伸区域的接触电阻，同时还可以减小栅极和漏极延伸区域之间的寄生电容。

62. 发明申请

US20120223331A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120223331A1
公开(公告)日：2012-09-06
申请号：US13063745
申请日：2011-03-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7849
摘要： A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.
摘要翻译：半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

63. 发明申请

US20120217553A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20120217553A1
公开(公告)日：2012-08-30
申请号：US13063737
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate formed on the substrate, and a source and drain formed in the substrate and disposed at two sides of the gate; raised portions formed on the source and the drain, respectively, a height of the raised portions being approximate to a height of the gate; and a metal silicide layer and contact holes formed on the raised portions and on the gate. By virtue of the raised portions added to the source/drain in an embodiment of the present invention, the height difference between the gate and the source/drain may be decreased, such that the formation of the contact holes becomes much easier.
摘要翻译：本发明提供一种半导体结构，包括：基板; 形成在基板上的栅极，以及形成在基板中并设置在栅极两侧的源极和漏极; 分别形成在源极和漏极上的凸起部分，凸起部分的高度接近门的高度; 以及形成在凸起部分和栅极上的金属硅化物层和接触孔。由于在本发明的一个实施例中，由于在源极/漏极上添加的凸起部分，栅极和源极/漏极之间的高度差可能会降低，使得接触孔的形成变得容易得多。

64. 发明授权

US08247278B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08247278B2
公开(公告)日：2012-08-21
申请号：US13201109
申请日：2011-03-03
申请人： Huilong Zhu , Chunlong Li , Jun Luo
发明人： Huilong Zhu , Chunlong Li , Jun Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance.
摘要翻译：本申请公开了一种用于制造半导体器件的方法，包括以下步骤：在第一绝缘层上依次形成半导体衬底，栅极堆叠和第二保护层; 在限定栅极区域并且在栅极区域外部去除第二保护层和栅极堆叠的部分之后，同时将覆盖图案化半导体层的侧壁的半导体层，半导体层和第二绝缘层的部分保持在栅极区域外部并暴露所述牺牲层，在所述半导体层中执行源/漏离子实现; 在形成第二侧壁间隔物以至少覆盖牺牲层的暴露部分之后，去除第一保护层和第二保护层以露出半导体层和栅极堆叠; 以及在所述半导体层和所述栅叠层的暴露部分上形成接触层; 进行平面化以使第一保护层露出，然后用第一侧壁间隔件和第二侧壁间隔件作为掩模去除第一保护层，牺牲层，停止层和半导体层，以形成空腔其暴露第一绝缘层。它有助于减少短沟道效应，源/漏区电阻和寄生电容。

65. 发明申请

US20120187496A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120187496A1
公开(公告)日：2012-07-26
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

66. 发明申请

US20120181664A1 SUBSTRATE STRUCTURE FOR SEMICONDUCTOR DEVICE FABRICATION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：用于半导体器件制造的衬底结构及其制造方法
公开(公告)号：US20120181664A1
公开(公告)日：2012-07-19
申请号：US13264063
申请日：2010-04-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/06 , H01L21/308 , H01L29/24 , H01L29/16
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.
摘要翻译：本发明提出一种带状板结构及其制造方法。在一个实施例中，带状板结构包括带板阵列，其包括以预定方向排列的多个带状板，每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向所述带状板结构的基本相反的侧面方向; 以及多个条状片，每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

67. 发明申请

US20120178232A1 FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT 审中-公开
标题翻译：现场效应装置结构包括自对准隔板形状接触
公开(公告)号：US20120178232A1
公开(公告)日：2012-07-12
申请号：US13427257
申请日：2012-03-22
申请人： Huilong Zhu
发明人： Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/76897 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L29/41775 , H01L29/42376 , H01L29/4966
摘要： A semiconductor structure and a method for fabricating the semiconductor structure include or provide a field effect device that includes a spacer shaped contact via. The spacer shaped contact via comprises a spacer shaped annular contact via that is located surrounding and separated from an annular spacer shaped gate electrode at the center of which may be located a non-annular and non-spacer shaped second contact via. The annular gate electrode as well as the annular contact via and the non-annular contact via may be formed sequentially in a self-aligned fashion while using a single sacrificial mandrel layer.
摘要翻译：半导体结构和制造半导体结构的方法包括或提供一种场效应器件，其包括间隔物形状的接触通孔。间隔件形状的接触通孔包括间隔件形状的环形接触通孔，该环形接触通孔位于围绕环形间隔件形状的栅极电极的周围并与之隔开，该环形间隔件形状的栅电极可以位于非环形和非隔离形状的第二接触通孔中。环形栅电极以及环形接触通孔和非环形接触通孔可以以自对准方式顺序地形成，同时使用单个牺牲心轴层。

68. 发明申请

US20120171842A1 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION 有权
标题翻译：应力生成具有双组分的浅层分离结构
公开(公告)号：US20120171842A1
公开(公告)日：2012-07-05
申请号：US13419927
申请日：2012-03-14
申请人： Huilong Zhu , Jing Wang
发明人： Huilong Zhu , Jing Wang
IPC分类号： H01L21/762
CPC分类号： H01L29/7846 , H01L21/3081 , H01L21/31053 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.
摘要翻译：提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率，第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

69. 发明申请

US20120168823A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168823A1
公开(公告)日：2012-07-05
申请号：US13377766
申请日：2011-04-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/26 , H01L21/66
CPC分类号： H01L21/823807 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/76229 , H01L21/823878 , H01L21/8258 , H01L29/66477
摘要： The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced.
摘要翻译：本申请公开了一种半导体器件及其形成方法。该方法包括：提供第一半导体层并在第一半导体层中形成第一STI; 确定所述第一半导体层中的选定区域，以及使所述选定区域中的所述第一半导体层的一部分凹陷; 并且在所选择的区域中，在第一半导体层上外延生长第二半导体层，其中第二半导体层的材料与第一半导体层的材料不同。根据本发明，可以通过简单的工艺形成具有选择性地外延生长并嵌入第一半导体层中的第二半导体层的结构，并且可以进一步减少在外延生长工艺期间产生的缺陷。

70. 发明申请

US20120104513A1 FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE 有权
标题翻译：具有非对称栅极电极的场效应晶体管
公开(公告)号：US20120104513A1
公开(公告)日：2012-05-03
申请号：US13344955
申请日：2012-01-06
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42376 , H01L21/28105 , H01L21/28114 , H01L21/28132 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66484 , H01L29/665 , H01L29/66613 , H01L29/7831
摘要： The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）的栅极包括源极侧栅电极和漏极侧栅电极，在栅极中间附近彼此邻接。在一个实施例中，源极侧栅极包括基于氧化硅的栅极电介质，漏极侧栅极包括高k栅极电介质。源极栅电极提供高载流子迁移率，而漏极侧栅电极提供良好的短沟道效应和减小的栅极泄漏。在另一个实施例中，源极栅极和漏极栅电极包括不同的高k栅极电介质堆叠和不同的栅极导体材料，其中源极侧栅电极具有远离带隙边缘的四分之一带隙的第一功函数和漏极侧栅电极在带隙边缘附近具有第二功函数。

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