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    • 61. 发明授权
    • Across-thread out of order instruction dispatch in a multithreaded graphics processor
    • 在多线程图形处理器中跨线程序指令调度
    • US07310722B2
    • 2007-12-18
    • US10742514
    • 2003-12-18
    • Simon S. MoyJohn Erik Lindholm
    • Simon S. MoyJohn Erik Lindholm
    • G06F9/38
    • G06F9/3802G06F9/3851
    • Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready to execute and may issue any ready instruction for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. Once an instruction from a particular thread has issued, the fetch circuit fills the available buffer location with the following instruction from that thread.
    • 诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。 指令被读取到指令缓冲区中,该缓冲器被配置为存储来自每个线程的指令。 调度电路确定缓冲器中的哪些指令准备好执行,并且可以发出任何可用的执行指令。 无论哪个指令首先被提取到缓冲区,可以在来自另一个线程的指令之前发出来自一个线程的指令。 一旦来自特定线程的指令已经发出,则获取电路使用该线程中的以下指令来填充可用的缓冲器位置。
    • 62. 发明授权
    • Software emulator for optimizing application-programmable vertex processing
    • 用于优化应用程序可编程顶点处理的软件仿真器
    • US07162716B2
    • 2007-01-09
    • US09877851
    • 2001-06-08
    • Robert Steven GlanvilleMark J. KilgardJohn Erik Lindholm
    • Robert Steven GlanvilleMark J. KilgardJohn Erik Lindholm
    • G06F9/45G06F13/14G06T15/00
    • G06T1/20
    • A central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) for performing graphics processing in accordance with a graphics processing standard. An extension to the software is included that identifies a first portion of the graphics processing to be performed on the graphics ASIC and a second portion of the graphics processing to be performed on the CPU. Such second portion of the graphics processing includes application-programmable vertex processing unavailable by the graphics ASIC. A compiler compiles the software to execute the first portion of the graphics processing on the graphics ASIC and the second portion of the graphics processing on the CPU in accordance with the extension.
    • 一种中央处理单元(CPU),包括用于执行能够对CPU执行图形处理的代码段的操作系统。 相关联的是用于根据图形处理标准执行图形处理的图形专用集成电路(ASIC)。 包括对软件的扩展,其标识要在图形ASIC上执行的图形处理的第一部分以及要在CPU上执行的图形处理的第二部分。 图形处理的这种第二部分包括由图形ASIC不可用的应用可编程顶点处理。 编译器编译该软件以执行图形ASIC上的图形处理的第一部分,并根据扩展在CPU上执行图形处理的第二部分。
    • 70. 发明授权
    • Programmable pixel shading architecture
    • 可编程像素着色架构
    • US06724394B1
    • 2004-04-20
    • US09885242
    • 2001-06-19
    • Harold Robert Feldman ZatzHenry P. MoretonJohn Erik Lindholm
    • Harold Robert Feldman ZatzHenry P. MoretonJohn Erik Lindholm
    • G06T1540
    • G06T15/50G06T15/005G06T15/60G06T15/80
    • A system and associated method are provided for processing pixel data in a graphics pipeline. Included is a triangle module coupled to a rasterizer for calculating a plurality of equations using pixel data received from the rasterizer. Also provided is a shader core module coupled to the rasterizer for receiving the pixel data therefrom. The shader core module is further coupled to the triangle module for receiving the equations therefrom. The shader core module functions to execute floating point calculations and generating texture coordinates using the pixel data. Coupled to the shader core module is a texture module. The texture module is capable of looking up texture values using the texture coordinates. Associated therewith is a shader back end module coupled to the texture module and the triangle module. The shader back end module is capable of converting the texture values to an appropriate floating point representation and generating color values using the equations. Still yet, a combiner module is coupled to the shader core module and the shader back end module. Such combiner module combines the color values and the texture values.
    • 提供了一种用于处理图形管线中的像素数据的系统和相关联的方法。 包括耦合到光栅化器的三角形模块,用于使用从光栅化器接收的像素数据来计算多个等式。 还提供了耦合到光栅化器的着色器核心模块,用于从其接收像素数据。 着色器核心模块还耦合到三角形模块以从其接收等式。 着色器核心模块用于执行浮点计算并使用像素数据生成纹理坐标。 结合着色器核心模块是一个纹理模块。 纹理模块能够使用纹理坐标查找纹理值。 与之相关联的是着色后端模块,其耦合到纹理模块和三角形模块。 着色器后端模块能够将纹理值转换为适当的浮点表示,并使用等式生成颜色值。 仍然,组合器模块耦合到着色器核心模块和着色器后端模块。 这样的组合器模块组合了颜色值和纹理值。