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61. 发明授权

US07298653B1 Reducing cross die variability in an EEPROM array 有权
标题翻译：减少EEPROM阵列中的交叉模具变化
公开(公告)号：US07298653B1
公开(公告)日：2007-11-20
申请号：US10873872
申请日：2004-06-21
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
摘要翻译：在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。

62. 发明授权

US07221608B1 Single NMOS device memory cell and array 有权
标题翻译：单个NMOS器件存储单元和阵列
公开(公告)号：US07221608B1
公开(公告)日：2007-05-22
申请号：US10957986
申请日：2004-10-04
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/403 , G11C2211/4065
摘要： The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.
摘要翻译： NMOS器件内的寄生NPN结构的快速恢复特性用于通过在高电压下使器件的自启动特性周期性地将器件从高阻抗状态触发到低阻抗状态来将信息写入和存储在器件中。为了最小化功率消耗并因此过热，在“导通”状态下，将脉冲模式操作与dV / dt触发相结合，以恒定的Vdd脉冲幅度向器件供电。

63. 发明授权

US07196361B1 Cascoded bi-directional high voltage ESD protection structure 有权
标题翻译： Cascoded双向高压ESD保护结构
公开(公告)号：US07196361B1
公开(公告)日：2007-03-27
申请号：US10734921
申请日：2003-12-12
申请人： Vladislav Vashchenko , Willem Kindt , Peter J. Hopper
发明人： Vladislav Vashchenko , Willem Kindt , Peter J. Hopper
IPC分类号： H01R29/747 , H01R29/87
CPC分类号： H01L27/0262
摘要： In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.
摘要翻译：在高电压ESD保护解决方案中，多个DIAC连接在一起以限定提供隔离区域的级联结构，以防止n阱和p阱穿通。一个p环环绕着DIAC，并为形成DIAC的衬底提供了一个接地。

64. 发明授权

US07180133B1 Method and structure for addressing hot carrier degradation in high voltage devices 有权
标题翻译：解决高压设备热载流子劣化的方法和结构
公开(公告)号：US07180133B1
公开(公告)日：2007-02-20
申请号：US11016147
申请日：2004-12-17
申请人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Yuri Mirgorodski , Philipp Lindorfer
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0619 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/7835
摘要： In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.
摘要翻译：在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。

65. 发明授权

US07145187B1 Substrate independent multiple input bi-directional ESD protection structure 有权
标题翻译：基板独立多输入双向ESD保护结构
公开(公告)号：US07145187B1
公开(公告)日：2006-12-05
申请号：US10735500
申请日：2003-12-12
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01L27/108 , H01L29/76 , H01L23/62 , H01L21/8238 , G11B5/33 , H02H9/00
CPC分类号： H01L29/747 , H01L27/0262
摘要： In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs are formed in a p-well which, in turn, is formed in a n-well. Each dual polarity input is isolated by a PBL under the p-well, and a NISO underneath the n-well. An isolation ring separates and surrounds the inputs. The isolation ring comprises a p+ ring or a p+ region, n+ region, and p+ region formed into adjacent rings.
摘要翻译：在多输入ESD保护结构中，输入通过与输入区域相反极性的高度掺杂区域与衬底隔离。通过提供形成每个双极性输入的n +和p +区域的对称结构来实现双极性。输入形成在p阱中，其又形成在n阱中。每个双极性输入由p-p下的PBL隔离，并在n阱下面隔开一个NISO。隔离环分隔并围绕输入。隔离环包括形成相邻环的p +环或p +区，n +区和p +区。

66. 发明授权

US07126168B1 Silicon controlled rectifier structures with reduced turn on times 有权
标题翻译：可控硅整流器结构，减少了开启次数
公开(公告)号：US07126168B1
公开(公告)日：2006-10-24
申请号：US10821287
申请日：2004-04-09
申请人： Vladislav Vashchenko , Peter J. Hopper
发明人： Vladislav Vashchenko , Peter J. Hopper
IPC分类号： H01L29/49
CPC分类号： H01L27/0262 , H01L29/87
摘要： The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn transistors, and a second step that, over time, fully turns on the structure.
摘要翻译：静电放电（ESD）结构的导通时间，例如可控硅整流器（SCR），低电压触发SCR（LVTSCR）和双极SCR（BSCR））通过打开两个结构步骤：第一步，在本地打开pnp和npn晶体管，第二步，随着时间的推移，完全打开结构。

67. 发明授权

US07115951B1 Low triggering voltage ESD protection structure and method for reducing the triggering voltage 有权
标题翻译：低触发电压ESD保护结构和降低触发电压的方法
公开(公告)号：US07115951B1
公开(公告)日：2006-10-03
申请号：US10234817
申请日：2002-09-04
申请人： Vladislav Vashchenko , Ann Concannon , Peter J. Hopper , Marcel ter Beek , Yuri Mirgorodsky
发明人： Vladislav Vashchenko , Ann Concannon , Peter J. Hopper , Marcel ter Beek , Yuri Mirgorodsky
IPC分类号： H01L23/62
CPC分类号： H01L29/4238 , H01L29/78
摘要： In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structure.
摘要翻译：在触发ESD保护结构中，通过将一个或多个拐角或尖峰引入p-n击穿结中来减小触发电压。这可以通过提供具有之字形图案的多晶硅浇口来在结构的漏极或阳极中限定三角形拐角来完成。

68. 发明授权

US07067852B1 Electrostatic discharge (ESD) protection structure 有权
标题翻译：静电放电（ESD）保护结构
公开(公告)号：US07067852B1
公开(公告)日：2006-06-27
申请号：US09660386
申请日：2000-09-12
申请人： Vladislav Vashchenko , Peter J. Hopper , Manuel Carneiro
发明人： Vladislav Vashchenko , Peter J. Hopper , Manuel Carneiro
IPC分类号： H01L29/74 , H01L23/62
CPC分类号： H01L27/0262 , H01L29/86 , H01L29/8618 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.
摘要翻译： ESD保护结构包括第一导电类型的半导体衬底和设置在衬底中的第二导电类型的第一和第二阱区。第一和第二阱区域被衬底的间隙区域分开。还包括设置在与间隙区域相邻的第一和第二阱区域中的第一和第二浮动区域（第二导电类型）。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区分开的第一导电类型的第一和第二接触区域。 ESD保护结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区隔开的第二导电类型的第一和第二接触区域。

69. 发明授权

US07064397B1 Silicon controlled rectifier structure with improved punch through resistance 有权
标题翻译：可控硅整流器结构，具有改善的穿通电阻
公开(公告)号：US07064397B1
公开(公告)日：2006-06-20
申请号：US10649989
申请日：2003-08-27
申请人： Vladislav Vashchenko , Peter J. Hopper , Ann Concannon , Marcel Ter Beek
发明人： Vladislav Vashchenko , Peter J. Hopper , Ann Concannon , Marcel Ter Beek
IPC分类号： H01L29/76
CPC分类号： H01L27/0262 , H01L29/87
摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.
摘要翻译：当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性通过在PNP晶体管的发射极和集电极之间形成NPN晶体管的集电极而大大减小。

70. 发明授权

US07037814B1 Single mask control of doping levels 有权
标题翻译：单掩模控制掺杂水平
公开(公告)号：US07037814B1
公开(公告)日：2006-05-02
申请号：US10683858
申请日：2003-10-10
申请人： Vladislav Vashchenko , Andy Strachan , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Andy Strachan , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L22/14 , H01L21/26513
摘要： In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the mask. The diffusion of dopant is completed by making use of an annealing stage.
摘要翻译：在集成电路中，通过使用穿孔掩模来调整掺杂剂浓度水平。跨越集成电路的不同区域的掺杂水平可以通过利用面罩中的穿孔的不同尺寸和间距而不同地限定。通过使用退火阶段完成掺杂剂的扩散。

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