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61. 发明申请

US20080148011A1 Carry/Borrow Handling 审中-公开
标题翻译：携带/借款处理
公开(公告)号：US20080148011A1
公开(公告)日：2008-06-19
申请号：US11610897
申请日：2006-12-14
申请人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
发明人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
IPC分类号： G06F9/30
CPC分类号： G06F9/3001
摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了用于执行进位/借用处理的系统和方法。根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

62. 发明申请

US20080144811A1 Method for Simultaneous Modular Exponentiations 有权
标题翻译：同时模块化指标的方法
公开(公告)号：US20080144811A1
公开(公告)日：2008-06-19
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

63. 发明申请

US20140156790A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 有权
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：US20140156790A1
公开(公告)日：2014-06-05
申请号：US13994129
申请日：2011-12-23
申请人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
发明人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
IPC分类号： H04L29/06
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

64. 发明申请

US20140082328A1 METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION 有权
标题翻译：过程4操作的方法和装置SIMD INTEGER MULTIPLY-ACCUMULATE指令
公开(公告)号：US20140082328A1
公开(公告)日：2014-03-20
申请号：US13617021
申请日：2012-09-14
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
IPC分类号： G06F9/302 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到基于第四操作数的累计值。

65. 发明授权

US09292297B2 Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction 有权
标题翻译：处理4操作数SIMD整数乘法累加指令的方法和装置
公开(公告)号：US09292297B2
公开(公告)日：2016-03-22
申请号：US13617021
申请日：2012-09-14
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
IPC分类号： G06F9/00 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到基于第四操作数的累计值。

66. 发明授权

US07925011B2 Method for simultaneous modular exponentiations 有权
标题翻译：同时采用模幂分析的方法
公开(公告)号：US07925011B2
公开(公告)日：2011-04-12
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

67. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

68. 发明申请

US20140093069A1 INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM 有权
标题翻译： SHA256算法的消息调度指令集
公开(公告)号：US20140093069A1
公开(公告)日：2014-04-03
申请号：US13631165
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译：处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

69. 发明申请

US20140093068A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

70. 发明申请

US20100161536A1 PATTERN MATCHING 有权
标题翻译：图案匹配
公开(公告)号：US20100161536A1
公开(公告)日：2010-06-24
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

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