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61. 发明授权

US08119158B2 Effervescent oral fentanyl dosage form and methods of administering fentanyl 有权
标题翻译：泡腾口服芬太尼剂型及施用芬太尼的方法
公开(公告)号：US08119158B2
公开(公告)日：2012-02-21
申请号：US12955346
申请日：2010-11-29
申请人： Derek Moe , Vikas Agarwal , Walib Habib
发明人： Derek Moe , Vikas Agarwal , Walib Habib
IPC分类号： A61K9/20 , A61K9/46
CPC分类号： A61K31/445 , A61K9/0007 , A61K9/006 , A61K9/205
摘要： Fentanyl-containing dosage forms and methods using same are described. These dosage forms include substantially less fentanyl by weight than known oral formulation and have advantages in terms of reduced cost and reduced side effects. These dosage forms are intended for oral administration of fentanyl across the oral mucosa.
摘要翻译：描述了含有芬太尼的剂型及使用它们的方法。这些剂型包括比已知口服制剂重量少的芬太尼，并且在降低成本和减少副作用方面具有优点。这些剂型旨在口服口服粘膜上的芬太尼。

62. 发明申请

US20110073518A1 Generally Linear Effervescent Oral Fentanyl Dosage Form and Methods of Administering 有权
标题翻译：一般线性泡腾口服芬太尼剂量形式和给药方法
公开(公告)号：US20110073518A1
公开(公告)日：2011-03-31
申请号：US12955229
申请日：2010-11-29
申请人： Derek Moe , Vikas Agarwal , Walid Habib
发明人： Derek Moe , Vikas Agarwal , Walid Habib
IPC分类号： A61K31/4468 , A61P29/00 , B65D83/04
CPC分类号： A61K31/445 , A61K9/0007 , A61K9/006 , A61K9/205
摘要： Fentanyl containing dosage forms and methods using same are described. These dosage forms include substantially less fentanyl by weight than know oral formulation and have advantages in terms of cost and side effects. These dosage forms are intended for oral administration of fentanyl across the oral mucosa.
摘要翻译：描述了含有芬太尼的剂型及使用它们的方法。这些剂型包括比已知口服制剂重量少的芬太尼，并且在成本和副作用方面具有优势。这些剂型旨在口服口服粘膜上的芬太尼。

63. 发明申请

US20110070169A1 Effervescent Oral Fentanyl Dosage Form and Methods of Administering Fentanyl 有权
标题翻译：泡腾口服芬太尼剂量形式和施用芬太尼的方法
公开(公告)号：US20110070169A1
公开(公告)日：2011-03-24
申请号：US12955346
申请日：2010-11-29
申请人： Derek Moe , Vikas Agarwal , Walib Habib
发明人： Derek Moe , Vikas Agarwal , Walib Habib
IPC分类号： A61K9/12 , A61K31/445 , A61P25/04
CPC分类号： A61K31/445 , A61K9/0007 , A61K9/006 , A61K9/205
摘要： Fentanyl-containing dosage forms and methods using same are described. These dosage forms include substantially less fentanyl by weight than known oral formulation and have advantages in terms of reduced cost and reduced side effects. These dosage forms are intended for oral administration of fentanyl across the oral mucosa.
摘要翻译：描述了含有芬太尼的剂型及使用它们的方法。这些剂型包括比已知口服制剂重量少的芬太尼，并且在降低成本和减少副作用方面具有优点。这些剂型旨在口服口服粘膜上的芬太尼。

64. 发明申请

US20100308663A1 ISOLATING FAULTY DECOUPLING CAPACITORS 有权
标题翻译：隔离故障解除电容器
公开(公告)号：US20100308663A1
公开(公告)日：2010-12-09
申请号：US12478477
申请日：2009-06-04
申请人： Vikas Agarwal , Sanjay Dubey , Ankit K. Gheedia , Nikhil Kejriwal , Sankara Reddy S. Kommareddi
发明人： Vikas Agarwal , Sanjay Dubey , Ankit K. Gheedia , Nikhil Kejriwal , Sankara Reddy S. Kommareddi
IPC分类号： H02J1/00
CPC分类号： G11C29/02 , G11C2029/5006 , H01L22/22
摘要： The present invention generally provides a decoupling capacitor circuit that is configured to determine whether a decoupling capacitor is defective. Upon determining that the decoupling capacitor is defective, the decoupling capacitor circuit may disconnect the decoupling capacitor from both, a positive segment and a negative segment of a power grid. In some embodiments, the decoupling capacitor circuit may be configured to reconnect the decoupling capacitor to the power grid upon receiving a reset signal.
摘要翻译：本发明通常提供一种去耦电容器电路，其被配置为确定去耦电容器是否有缺陷。在确定去耦电容器有缺陷时，去耦电容器电路可以将去耦电容器与电网的正段和负段断开。在一些实施例中，解耦电容器电路可以被配置为在接收到复位信号时将去耦电容器重新连接到电网。

65. 发明授权

US07545176B2 Energy-saving circuit and method using charge equalization across complementary nodes 失效
标题翻译：节能电路和方法在互补节点上使用电荷均衡
公开(公告)号：US07545176B2
公开(公告)日：2009-06-09
申请号：US11923714
申请日：2007-10-25
申请人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
发明人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K5/151 , H03K19/0008
摘要： An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
摘要翻译：在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗，例如具有互补高电容节点的宽多路复用器。改变检测电路检测要施加到位线的状态变化，并且如果要施加状态改变则产生脉冲。连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。驱动电路使能输入也被延迟，使得位线不被驱动，直到电荷被均衡并且通路禁止。在一个实施例中，驱动器电路仅通过变化检测器的脉冲输出暂时使能，并且使用保持器电路将位线保持在其断言状态。

66. 发明申请

US20090108920A1 ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES 失效
标题翻译：节能电路和使用充电均衡的方法
公开(公告)号：US20090108920A1
公开(公告)日：2009-04-30
申请号：US11923714
申请日：2007-10-25
申请人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
发明人： Vikas Agarwal , Sanjay Dubey , Saiful Islam , Gaurav Mittal
IPC分类号： G05F1/10
CPC分类号： H03K5/151 , H03K19/0008
摘要： An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states.
摘要翻译：在互补节点上使用电荷均衡的节能电路和方法降低存储器电路和其它电路中的功耗，例如具有互补高电容节点的宽多路复用器。改变检测电路检测要施加到位线的状态变化，并且如果要施加状态改变则产生脉冲。连接在节点之间的通过门被响应于脉冲激活以均衡位线上的电荷。驱动电路使能输入也被延迟，使得位线不被驱动，直到电荷被均衡并且通路禁止。在一个实施例中，驱动器电路仅通过变化检测器的脉冲输出暂时使能，并且使用保持器电路将位线保持在其断言状态。

67. 发明授权

US07509414B2 System and method for collection, aggregation, and composition of metrics 失效
标题翻译：用于收集，聚合和组合度量的系统和方法
公开(公告)号：US07509414B2
公开(公告)日：2009-03-24
申请号：US10976941
申请日：2004-10-29
申请人： Vikas Agarwal , William P. Horn , Arun Kumar
发明人： Vikas Agarwal , William P. Horn , Arun Kumar
IPC分类号： G06F15/173
CPC分类号： G06Q30/02 , G06F9/546
摘要： A method for collecting, aggregating, and composing metrics and a computer system comprises a producer application adapted to periodically generate metrics comprising state information of the producer application; a metric engine adapted to aggregate the metrics; and a consumer application adapted to receive the aggregated metrics, wherein the metric engine is further adapted to produce new metrics in accordance with desired requirements of the consumer application. The computer system further comprises a metric service policy adapted to provide definitions of the metrics generated from the producer application and desired requirements of the consumer application, wherein the metric service policy is adapted to establish an executable set of actions for producing the new metrics from the generated metrics, wherein the metric service policy is adapted to be executable by the metric engine, and wherein multiple metric service policies are simultaneously executable by the metric engine.
摘要翻译：用于收集，聚合和组合度量的方法以及计算机系统包括适于周期性地生成包括生产者应用的状态信息的度量的生成器应用; 适于聚合度量的度量引擎; 以及适于接收所述聚合度量的消费者应用，其中所述度量引擎还适于根据所述消费者应用的期望要求产生新的度量。计算机系统还包括适于提供从生产者应用程序产生的度量的定义和消费者应用程序的期望需求的度量服务策略，其中度量服务策略适于建立可执行的一组动作，用于从其中所述度量服务策略适于由所述度量引擎执行，并且其中多个度量服务策略可由所述度量引擎同时执行。

68. 发明申请

US20080251888A1 Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits 失效
标题翻译：集成电路中自包含自动去耦电容开关的方法和装置
公开(公告)号：US20080251888A1
公开(公告)日：2008-10-16
申请号：US11733435
申请日：2007-04-10
申请人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
发明人： Vikas Agarwal , Asit S. Ambekar , Sanjay Dubey , Saiful Islam
IPC分类号： H01L27/02
CPC分类号： H01L27/0805 , G06F1/26 , H01L27/0629 , Y10T307/865
摘要： An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.
摘要翻译：集成电路（IC）包括耦合到电源的电源互连。集成电路包括执行所需功能的电子器件，还包括在整个集成电路中提供降噪的去耦电容器电路。在一个实施例中，每个去耦电容器电路包括去耦电容器和开关电路。当开关电路检测到没有实质的去耦电容器泄漏时，开关电路在连接模式期间将去耦电容器连接到电源互连。然而，当开关电路检测到实质的去耦电容器泄漏时，开关电路在断开模式期间有效地将去耦电容器与电源互连件断开。去耦电容电路在连接模式下自我初始化，无需外部控制信号，因此是独立的。由于去耦电容电路的自包含性质，集成电路可能包含一个去耦电容电路的阵列，而不需要相应的去耦电容器控制线的大量芯片空间。

69. 发明申请

US20080133764A1 Apparatus, Methods and Computer Programs for Metering and Accounting for Services Accessed Over a Network 有权
标题翻译：用于通过网络访问的服务的计量和计费的装置，方法和计算机程序
公开(公告)号：US20080133764A1
公开(公告)日：2008-06-05
申请号：US12015160
申请日：2008-01-16
申请人： Vikas Agarwal , Neeran M. Karnik , Arun Kumar
发明人： Vikas Agarwal , Neeran M. Karnik , Arun Kumar
IPC分类号： G06F15/16
CPC分类号： G06Q20/102 , G06F11/34 , G06Q30/00 , G06Q30/0283 , G06Q30/04 , G06Q40/02 , G06Q40/12 , H04L12/14 , H04L12/1428 , H04L12/1432 , H04L41/00 , H04L43/00 , H04L63/00 , H04L65/1096 , H04L67/22
摘要： Apparatus, methods and computer programs provided for metering and accounting in a commercial e-services infrastructure address the requirement for handling composite services in which higher-level services are built using simpler underlying services, each of which may be autonomously owned and operated. Metering records for each service underlying a composite service are correlated by a process associated with the composite service, and then sent to an accounting service where they can be aggregated. The correlation is performed in a distributed manner with correlated usage data provided on a per-request basis. Accounting services can take account of the usage and charges associated with the underlying services to provide accounting and billing on a per-request basis or per customer-provider pair for a billing period.
摘要翻译：在商业电子服务基础设施中提供的用于计量和计费的设备，方法和计算机程序解决了处理复合服务的需求，其中使用更简单的底层服务构建更高层次的服务，每个服务可以是自主拥有和操作的。组合服务底层的每个服务的计费记录由与组合服务关联的进程相关，然后发送到可以聚合的会计服务。相关性以分布式方式执行，其中每个请求都提供相关的使用数据。会计服务可以考虑与基础服务相关联的使用和费用，以便在每个请求的基础上提供会计和计费，或者在每个客户 - 提供者对中进行结算周期。

70. 发明申请

US20070245279A1 Method and System for Verifying Performance of an Array by Simulating Operation of Edge Cells in a Full Array Model 有权
标题翻译：通过在全阵列模型中模拟边缘单元的操作来验证阵列性能的方法和系统
公开(公告)号：US20070245279A1
公开(公告)日：2007-10-18
申请号：US11279312
申请日：2006-04-11
申请人： Vikas Agarwal , Michael Hyeok Lee , Philip Shephard
发明人： Vikas Agarwal , Michael Hyeok Lee , Philip Shephard
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译：通过模拟全阵列模型中的边缘单元的操作来验证阵列的性能的方法和系统减少了完整设计验证所需的计算时间。阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。观察到字线到达以确定最坏情况行进行选择。对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。

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