专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US6100158A Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region 有权
标题翻译：制造具有蚀刻背面介电层和透明电介质层的对准标记的方法和具有布线层和隔离区域的较高平面上的器件区域
公开(公告)号：US6100158A
公开(公告)日：2000-08-08
申请号：US302884
申请日：1999-04-30
申请人： Tzung-Han Lee , Kun-Chi Lin , Horng-Nan Chern , Alex Hou
发明人： Tzung-Han Lee , Kun-Chi Lin , Horng-Nan Chern , Alex Hou
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.
摘要翻译：制造对准标记的方法。提供具有器件区域和对准标记区域的衬底。器件区域高于对准标记区域。器件区域包括有源区。在对准标记区域的边缘处的基板中形成隔离结构，同时在对准标记区域的一部分基板上形成第一电介质层。导电层形成在衬底上。去除导电层的一部分以在对准标记区域露出第一介电层。将剩余的导电层图案化以在有源区域形成部件。在衬底上形成具有光滑表面的第二电介质层以覆盖该部件。在第二电介质层上形成导线，其中导线与对准标记区域之间的距离大于部件与对准标记区域之间的距离。

62. 发明授权

US6040241A Method of avoiding sidewall residue in forming connections 失效
标题翻译：避免侧壁残留物形成连接的方法
公开(公告)号：US6040241A
公开(公告)日：2000-03-21
申请号：US21750
申请日：1998-02-11
申请人： Tzung-Han Lee , Horng-Nan Chern
发明人： Tzung-Han Lee , Horng-Nan Chern
IPC分类号： H01L21/28 , H01L21/768 , H01L21/336
CPC分类号： H01L21/76885 , H01L21/28061 , H01L21/76801
摘要： The method in the present invention for forming insulation over conductor includes the following steps. At first, a substrate with a first conductor formed over is provided. The first conductor can be either a gate structure or an interconnection layer. A dielectric layer is then formed over the first conductor the substrate. A portion of the dielectric layer is removed for having a recess free sidewall on the dielectric layer around the first conductor. An insulation for succeeding conductive layer is formed.
摘要翻译：用于形成导体绝缘的本发明中的方法包括以下步骤。首先，提供形成有第一导体的基板。第一导体可以是栅极结构或互连层。然后在衬底的第一导体上形成电介质层。去除介电层的一部分，以在第一导体周围的介电层上具有无凹槽的侧壁。形成用于后续导电层的绝缘体。

63. 发明授权

US5933749A Method for removing a top corner of a trench 失效
标题翻译：去除沟槽顶角的方法
公开(公告)号：US5933749A
公开(公告)日：1999-08-03
申请号：US964
申请日：1997-12-30
申请人： Tzung-Han Lee
发明人： Tzung-Han Lee
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05 , Y10S438/978
摘要： A method for removing the top corner of the trench is disclosed. After the formation of an oxide layer and then a nitride layer over a substrate, a portion of the nitride layer, the oxide layer and the substrate are removed to form a trench. A mask is next formed on the nitride layer, wherein the opening of the mask is larger than the corresponding trench. A dry etching is performed to etch the exposed nitride layer and the substrate, using said mask. After removing the mask and the nitride layer, a liner oxide layer is then formed. The dry etching process removes the top corner to form a grading corner which consequently avoids charge accumulation and point discharging.
摘要翻译：公开了一种去除沟槽顶角的方法。在衬底上形成氧化物层，然后形成氮化物层之后，去除氮化物层，氧化物层和衬底的一部分以形成沟槽。接着在氮化物层上形成掩模，其中掩模的开口大于相应的沟槽。使用所述掩模进行干蚀刻以蚀刻暴露的氮化物层和衬底。在去除掩模和氮化物层之后，形成衬里氧化物层。干蚀刻工艺去除顶角以形成分级角，从而避免电荷积聚和点放电。

64. 发明授权

US08604620B2 Semiconductor structure having lateral through silicon via 有权
标题翻译：具有横向硅通孔的半导体结构
公开(公告)号：US08604620B2
公开(公告)日：2013-12-10
申请号：US13342201
申请日：2012-01-03
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/94 , H01L25/0657 , H01L2224/02371 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/08145 , H01L2224/08148 , H01L2224/94 , H01L2225/06551 , H01L2225/06565 , H01L2224/03
摘要： The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.
摘要翻译：本发明提供一种具有横向TSV的半导体结构及其制造方法。半导体结构包括具有有源侧的芯片，与有源侧相对设置的背面以及设置在主动侧和后侧之间的侧面。芯片还包括接触焊盘，横向TSV和图案化导电层。接触垫设置在活动侧。横向TSV设置在侧面。图案化导电层设置在有源侧上并且电连接到侧向TSV和接触焊盘。

65. 发明申请

US20130113110A1 Semiconductor Structure Having Lateral Through Silicon Via And Manufacturing Method Thereof 有权
标题翻译：具有横向通过硅的半导体结构及其制造方法
公开(公告)号：US20130113110A1
公开(公告)日：2013-05-09
申请号：US13342201
申请日：2012-01-03
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
IPC分类号： H01L23/48 , H01L21/78
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/94 , H01L25/0657 , H01L2224/02371 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05666 , H01L2224/0568 , H01L2224/05681 , H01L2224/08145 , H01L2224/08148 , H01L2224/94 , H01L2225/06551 , H01L2225/06565 , H01L2224/03
摘要： The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.
摘要翻译：本发明提供一种具有横向TSV的半导体结构及其制造方法。半导体结构包括具有有源侧的芯片，与有源侧相对设置的背面以及设置在主动侧和后侧之间的侧面。芯片还包括接触焊盘，横向TSV和图案化导电层。接触垫设置在活动侧。横向TSV设置在侧面。图案化导电层设置在有源侧上并且电连接到侧向TSV和接触焊盘。

66. 发明授权

US08431933B2 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US08431933B2
公开(公告)日：2013-04-30
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L29/10
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

67. 发明授权

US07524205B1 Conducting wire anti-drop structure 失效
标题翻译：导线防滴结构
公开(公告)号：US07524205B1
公开(公告)日：2009-04-28
申请号：US12145114
申请日：2008-06-24
申请人： Tzung-Han Lee
发明人： Tzung-Han Lee
IPC分类号： H01R13/64
CPC分类号： H01R13/6392
摘要： The present invention is related to a conducting wire anti-drop structure for fixing two mutually connected conducting wires, which respectively have a connecting terminal for connecting with each other. The conducting wire anti-drop structure is characterized in that a positioning device is mounted on the connecting terminal of one of the conducting wires and has a positioning portion. The positioning portion is used to connect with a position-limiting device, which has an engaging portion extended from the connecting terminal for engaging with the other connecting terminal so as to limit the connection between the connecting terminals and provide stability.
摘要翻译：本发明涉及用于固定两个相互连接的导线的导线防滴结构，它们分别具有用于彼此连接的连接端子。导线防滴结构的特征在于，定位装置安装在一根导线的连接端子上，并具有定位部分。定位部用于与限位装置连接，该位置限制装置具有从连接端子延伸的接合部分，用于与另一连接端子接合，以限制连接端子之间的连接并提供稳定性。

68. 发明申请

US20080299734A1 Method of manufacturing a self-aligned fin field effect transistor (FinFET) device 审中-公开
标题翻译：制造自对准鳍状场效应晶体管（FinFET）器件的方法
公开(公告)号：US20080299734A1
公开(公告)日：2008-12-04
申请号：US11934044
申请日：2007-11-01
申请人： Tzung-Han Lee , Chin-Tien Yang
发明人： Tzung-Han Lee , Chin-Tien Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66818
摘要： A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched, allowing the semiconductor substrate to form into a relatively thin fin structure for forming a three-dimensional gate structure having three faces.
摘要翻译：公开了一种制造自对准翅片FET（FinFET）器件的方法，其中将浅沟槽隔离的绝缘层回蚀刻以部分地暴露由浅沟槽隔离包围的半导体衬底的侧壁，并且侧壁然后各向同性蚀刻半导体衬底，使得半导体衬底形成相对薄的鳍结构，以形成具有三个面的三维栅极结构。

69. 发明授权

US07449741B2 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US07449741B2
公开(公告)日：2008-11-11
申请号：US11416699
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

70. 发明授权

US07309890B2 SRAM cell structure and manufacturing method thereof 有权
标题翻译： SRAM单元结构及其制造方法
公开(公告)号：US07309890B2
公开(公告)日：2007-12-18
申请号：US11416925
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L31/119
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.
摘要翻译：至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。在衬底中设置器件隔离结构以限定有源区。活动区域有一个开口。晶体管设置在衬底的有源区上。晶体管的源极区域靠近开口。将上电极设置在开口上方，使得开口完全充满。电容器介电层设置在上电极和衬底之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式