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61. 发明申请

US20050142815A1 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20050142815A1
公开(公告)日：2005-06-30
申请号：US11020049
申请日：2004-12-23
申请人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
发明人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
IPC分类号： H01L21/301 , H01L21/304 , H01L21/306 , H01L21/314 , H01L21/316 , H01L21/46 , H01L21/52 , H01L21/60 , H01L21/68 , H01L21/78 , H01L21/82
CPC分类号： H01L21/6835 , H01L21/02238 , H01L21/02255 , H01L21/30625 , H01L21/314 , H01L21/31654 , H01L21/31675 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
摘要翻译：一种能够从切割带稳定地释放芯片的技术包括：将压敏粘合带粘附到形成有集成电路的半导体晶片的电路形成表面上，研磨半导体晶片的背面，以实现预定厚度，强制氧化半导体晶片的背面。然后，剥离粘附到半导体晶片的电路形成表面的压敏粘合带，并将切割带粘附到半导体晶片的背面。此外，通过将半导体晶片切割成单独的芯片来分割半导体晶片，然后通过切割带对芯片的背面进行压制，从而从切割带释放芯片。

62. 发明申请

US20050087219A1 Ultrasonic shower cleaning apparatus of double-side cleaning type 有权
标题翻译：双面清洗型超声波淋浴清洗设备
公开(公告)号：US20050087219A1
公开(公告)日：2005-04-28
申请号：US10909187
申请日：2004-07-30
申请人： Seigo Takahashi , Junpei Ohkawara , Kazunari Suzuki
发明人： Seigo Takahashi , Junpei Ohkawara , Kazunari Suzuki
IPC分类号： B08B3/12 , B08B3/02
CPC分类号： B08B3/02 , B08B2203/0288 , Y10S134/902
摘要： An ultrasonic shower cleaning apparatus is disclosed which is capable of efficiently cleaning both surfaces of an article and configured to have a reduced size enabling an installation space thereof to be decreased. A pair of ultrasonic shower cleaning mechanisms each include a nozzle, a disc-shaped ultrasonic transducer arranged so as to face a backward end of the nozzle and an inlet port for a cleaning liquid formed opposite to a side surface of the nozzle. The ultrasonic shower cleaning mechanisms are integrally incorporated in one casing in such a manner that axes of the nozzles cross each other at a predetermined angle. The casing is provided with one inlet branch port connected to the inlet ports of the ultrasonic shower cleaning mechanisms. The casing may have a groove formed therein in which an edge of the article arranged between the two nozzles can be inserted.
摘要翻译：公开了一种超声波淋浴清洗装置，其能够有效地清洁物品的两个表面并且被配置为具有能够减小其安装空间的减小的尺寸。一对超声波淋浴清洗机构各自包括喷嘴，布置成面对喷嘴的后端的盘形超声波换能器和与喷嘴的侧表面相对地形成的清洁液的入口。超声波清洗机构以一定的角度相互交叉的方式一体地结合在一个壳体中。壳体设置有连接到超声波淋浴清洗机构的入口的一个入口分支端口。壳体可以具有形成在其中的凹槽，其中可以插入布置在两个喷嘴之间的物品的边缘。

63. 发明授权

US06723583B2 Method of manufacturing a semiconductor device using a mold 有权
标题翻译：使用模具制造半导体器件的方法
公开(公告)号：US06723583B2
公开(公告)日：2004-04-20
申请号：US10453606
申请日：2003-06-04
申请人： Noriyuki Takahashi , Masayuki Suzuki , Kouji Tsuchiya , Takao Matsuura , Takanori Hashizume , Masahiro Ichitani , Kazunari Suzuki , Takafumi Nishita , Kenichi Imura , Takashi Miwa
发明人： Noriyuki Takahashi , Masayuki Suzuki , Kouji Tsuchiya , Takao Matsuura , Takanori Hashizume , Masahiro Ichitani , Kazunari Suzuki , Takafumi Nishita , Kenichi Imura , Takashi Miwa
IPC分类号： H01L2144
CPC分类号： H01L23/564 , H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2223/5442 , H01L2223/54473 , H01L2224/16 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/92 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/20752 , H01L2924/30105 , H01L2924/351 , H01L2224/83 , H01L2224/85 , H01L2924/00014 , H01L2224/92247 , H01L2924/00 , H01L2924/00012
摘要： The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.
摘要翻译：将其上安装有多个半导体芯片的带状基板的背面真空吸附到模具的下半模，并且在该状态下，多个半导体芯片同时用树脂密封以形成密封构件。此后，带状基板和密封构件从模具中释放并切割成多个半导体器件。由此获得的半导体器件的安装可靠性得到改善。

64. 发明授权

US06692989B2 Plastic molded type semiconductor device and fabrication process thereof 失效
标题翻译：塑料模制型半导体器件及其制造方法
公开(公告)号：US06692989B2
公开(公告)日：2004-02-17
申请号：US10371275
申请日：2003-02-24
申请人： Yoshinori Miyaki , Hiromichi Suzuki , Kazunari Suzuki , Takafumi Nishita , Fujio Ito , Kunihiro Tsubosaki , Akihiko Kameoka , Kunihiko Nishi
发明人： Yoshinori Miyaki , Hiromichi Suzuki , Kazunari Suzuki , Takafumi Nishita , Fujio Ito , Kunihiro Tsubosaki , Akihiko Kameoka , Kunihiko Nishi
IPC分类号： H01L2144
CPC分类号： H01L24/32 , H01L21/565 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/06179 , H01L2224/29007 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/01026 , H01L2924/01028 , H01L2924/00012 , H01L2924/00 , H01L2924/3512
摘要： A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold. The semiconductor chip and the die pad are disposed within a cavity of a mold so that the clearance from the reverse surface of the die pad to the inside wall surface of the cavity opposite to the reverse surface of the die pad becomes narrower, by a length corresponding to the thickness of the die pad, than the clearance from the principal surface of the semiconductor chip to the inside wall surface of the cavity opposite to the principal surface of the semiconductor chip; and a resin is poured from a center gate into said cavity to form a plastic mold, which makes it possible to prevent said semiconductor chip from being lifted upwardly by the resin flowing in a filling region on the reverse surface side of the semiconductor chip. As a result, inconvenient shifting of the semiconductor chip, bonding wires and the like in the plastic mold can be prevented, leading to an increase in the yield of the plastic molded type semiconductor device.
摘要翻译：提供了一种用于制造塑料模制型半导体器件的工艺，其中芯片焊盘形成为具有比要安装在管芯焊盘的主表面上的半导体芯片更小的面积，并且半导体芯片和管芯焊盘被密封用塑料模具。半导体芯片和芯片焊盘设置在模具的腔内，使得从芯片焊盘的反面到与模具垫的反面相反的腔的内壁表面的间隙变窄，长度与半导体芯片的主表面到与半导体芯片的主表面相对的腔的内壁表面的间隙相对应于芯片焊盘的厚度; 并且将树脂从中心浇口注入所述空腔中以形成塑料模具，这使得可以防止所述半导体芯片被在半导体芯片的反面上的填充区域中流动的树脂向上提升。结果，可以防止半导体芯片，接合线等在塑料模具中的不方便的移动，导致塑料模制型半导体器件的产量的增加。

65. 发明授权

US06673655B2 Method of making semiconductor device having improved heat radiation plate arrangement 失效
标题翻译：制造具有改进的散热板布置的半导体器件的方法
公开(公告)号：US06673655B2
公开(公告)日：2004-01-06
申请号：US10152726
申请日：2002-05-23
申请人： Fujio Ito , Hiroaki Tanaka , Hiromichi Suzuki , Tokuji Toida , Takafumi Konno , Kunihiro Tsubosaki , Shigeki Tanaka , Kazunari Suzuki , Akihiko Kameoka
发明人： Fujio Ito , Hiroaki Tanaka , Hiromichi Suzuki , Tokuji Toida , Takafumi Konno , Kunihiro Tsubosaki , Shigeki Tanaka , Kazunari Suzuki , Akihiko Kameoka
IPC分类号： H01L2348
CPC分类号： H01L24/32 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/49171 , H01L2224/49431 , H01L2224/49433 , H01L2224/73265 , H01L2224/85385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/01026 , H01L2924/00012 , H01L2924/3512 , H01L2224/85399 , H01L2224/05599
摘要： In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w
摘要翻译：在具有散热板的半导体器件中，连接到半导体芯片的内部引线的尖端具有引线宽度w和引线厚度t，宽度小于厚度。内引线固定在散热板上。将内部引线固定到散热板上，支撑后者，并且不需要悬挂引线。引线间距p，连接到半导体芯片的内引线头的引线宽度w和引线厚度t具有w

66. 发明授权

US06372554B1 Semiconductor integrated circuit device and method for production of the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06372554B1
公开(公告)日：2002-04-16
申请号：US09390682
申请日：1999-09-07
申请人： Keizo Kawakita , Kazuhiko Kajigaya , Seiji Narui , Kiyoshi Nakai , Kazunari Suzuki , Hideaki Tsugane , Fumiyoshi Sato
发明人： Keizo Kawakita , Kazuhiko Kajigaya , Seiji Narui , Kiyoshi Nakai , Kazunari Suzuki , Hideaki Tsugane , Fumiyoshi Sato
IPC分类号： H01L2182
CPC分类号： H01L27/10894 , H01L23/5258 , H01L27/10814 , H01L28/84 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.
摘要翻译：覆盖在TEG区域中形成的熔丝的多于一个的导电层的图案经过OR处理; 此外，通过转印技术将连接到所述熔丝的一个或多个测试焊盘的开口图案的组合或“合成”图案复制到涂覆在半导体晶片的表面上的感光性树脂层，从而迫使树脂层仅驻留在划线区域的选定区域中，合成图案已转移到该区域。

67. 发明授权

US09237091B2 System and method of load balancing for ethernet link aggregation 有权
标题翻译：以太网链路聚合的负载均衡的系统和方法
公开(公告)号：US09237091B2
公开(公告)日：2016-01-12
申请号：US13529371
申请日：2012-06-21
申请人： Masakazu Sato , Satoshi Nakajima , Kazunari Suzuki
发明人： Masakazu Sato , Satoshi Nakajima , Kazunari Suzuki
IPC分类号： H04L12/931 , H04L12/709 , H04L29/12 , H04W84/18 , H04L12/413 , H04L12/741 , H04L29/06
CPC分类号： H04L45/245 , H04L12/413 , H04L45/745 , H04L49/351 , H04L61/2092 , H04L69/22 , H04W84/18 , Y02D50/30
摘要： A system and method of transmitting data across a first link aggregation formed by an intermediate switch and a downstream switch, the intermediate switch adopting a Media-Access Card (MAC)-address-based load sharing algorithm for distributing traffic among links to the downstream switch interfaced with a final destination device. The method comprises: receiving a packet having a MAC header and an IP header at an input port of an upstream switch for transmission from the upstream switch to the intermediate switch, the upstream switch and intermediate switch forming a second link aggregation; re-writing, at the upstream switch, the source MAC address of the received packet to a different source address; sending the packet through the second link aggregation to the intermediate switch, the intermediate switch implementing the load sharing algorithm for sending the packet to the downstream switch along a link through the first link aggregation to the destination device.
摘要翻译：一种通过中间交换机和下游交换机形成的第一链路聚合发送数据的系统和方法，所述中间交换机采用基于媒体接入卡（MAC）地址的负载分担算法，用于在下游交换机的链路之间分配业务与最终目的地设备连接。该方法包括：在上游交换机的输入端口接收具有MAC报头和IP报头的分组，从上游交换机向中间交换机发送，上游交换机和中间交换机形成第二链路聚合; 在上游交换机上重新写入接收到的数据包的源MAC地址到不同的源地址; 将所述分组通过所述第二链路聚合发送到所述中间交换机，所述中间交换机实现负载分担算法，用于通过所述第一链路聚合向所述目的设备沿着链路向所述下游交换机发送所述分组。

68. 发明授权

US08378459B2 Semiconductor device, semiconductor wafer and manufacturing method of the same 失效
标题翻译：半导体器件，半导体晶片及其制造方法
公开(公告)号：US08378459B2
公开(公告)日：2013-02-19
申请号：US12795950
申请日：2010-06-08
申请人： Yasuhiro Naka , Naotaka Tanaka , Toshihide Uematsu , Chuichi Miyazaki , Kazunari Suzuki , Yasuyuki Nakajima , Yoshiyuki Abe , Kenji Kohzu , Kosuke Kitaichi , Shinya Ogane
发明人： Yasuhiro Naka , Naotaka Tanaka , Toshihide Uematsu , Chuichi Miyazaki , Kazunari Suzuki , Yasuyuki Nakajima , Yoshiyuki Abe , Kenji Kohzu , Kosuke Kitaichi , Shinya Ogane
IPC分类号： H01L23/544
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/05644 , H01L2224/06102 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01052 , H01L2924/01055 , H01L2924/01056 , H01L2924/01064 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10158 , H01L2924/1306 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2924/00014
摘要： In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
摘要翻译：在粘合带附着到半导体晶片的主表面上的状态下，在半导体晶片的后表面上形成沟槽。为了在半导体晶片的后表面中形成沟槽，在半导体晶片的后表面上涂覆抗蚀剂膜之后，通过使用光刻技术对抗蚀剂膜进行构图。进行抗蚀剂膜的图案化，以便不在要形成沟槽的区域中留下抗蚀剂膜。然后，通过使用图案化的抗蚀剂膜作为掩模的干蚀刻技术，在半导体晶片的预定区域中形成沟槽。具体地说，在切割线附近的区域形成沟槽。

69. 发明授权

US08274980B2 Ethernet link aggregation 失效
标题翻译：以太网链路聚合
公开(公告)号：US08274980B2
公开(公告)日：2012-09-25
申请号：US12393727
申请日：2009-02-26
申请人： Masakazu Sato , Satoshi Nakajima , Kazunari Suzuki
发明人： Masakazu Sato , Satoshi Nakajima , Kazunari Suzuki
IPC分类号： H04L12/56
CPC分类号： H04L45/245 , H04L12/413 , H04L45/745 , H04L49/351 , H04L61/2092 , H04L69/22 , H04W84/18 , Y02D50/30
摘要： A system and method of transmitting data across a link aggregation group, the method comprises: receiving a packet sourced from a client having a MAC header and an IP header at an input port of a first upstream switch for transmission from the first upstream switch along a link aggregation and at least two down stream switches to a server, said MAC header having a Destination MAC address and a Source MAC address, and the IP header having a Source IP address and a Destination IP address; changing the destination MAC address from a down stream destination to another down stream destination; sending the packet through a first link aggregation to a first down stream switch; using a hash calculation for changing the Source MAC address of the packet in the first down stream switch to a new address; sending the packet through a second link aggregation to a second down stream switch having an address; and sending the packet from the second down stream switch to a server having a server address.
摘要翻译：一种通过链路聚合组发送数据的系统和方法，所述方法包括：从第一上游交换机的输入端口接收来自具有MAC报头和IP报头的客户端的分组，以从第一上游交换机沿着链路聚合和至少两个下行切换到服务器，所述MAC报头具有目的地MAC地址和源MAC地址，所述IP报头具有源IP地址和目的地IP地址; 将目的MAC地址从下行目的地改变到另一下行目的地; 通过第一链路聚合将分组发送到第一下行链路交换机; 使用哈希计算来将第一下行切换中的分组的源MAC地址改变为新的地址; 通过第二链路聚合将分组发送到具有地址的第二下行交换机; 并将分组从第二下行交换机发送到具有服务器地址的服务器。

70. 再颁专利

USRE43443E1 Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two 有权
标题翻译：使用其的引线框半导体集成电路器件及其制造方法和工艺
公开(公告)号：USRE43443E1
公开(公告)日：2012-06-05
申请号：US09987978
申请日：2001-11-16
申请人： Yujiro Kajihara , Kazunari Suzuki , Kunihiro Tsubosaki , Hiromichi Suzuki , Yoshinori Miyaki , Takahiro Naito , Sueo Kawai
发明人： Yujiro Kajihara , Kazunari Suzuki , Kunihiro Tsubosaki , Hiromichi Suzuki , Yoshinori Miyaki , Takahiro Naito , Sueo Kawai
IPC分类号： H01L23/495
CPC分类号： H01L24/743 , H01L21/4842 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L2224/02166 , H01L2224/29007 , H01L2224/2919 , H01L2224/32014 , H01L2224/32055 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/743 , H01L2224/82181 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/85181 , H01L2224/859 , H01L2224/92 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
摘要翻译：为了提高回流焊时的LSI封装的封装体抗开裂性，并且提供适用于制造根据柔性制造系统的LSI封装的引线框和使用引线框的LSI，半导体芯片2 并且通过使管芯焊盘3的外部尺寸小于要安装在其上的半导体芯片的外部尺寸来扩大树脂。此外，通过根据半导体芯片2的外部尺寸将引线5的前端切割成合适的长度，可以将不同的外部尺寸的各种半导体芯片2安装在管芯焊盘3上。

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