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61. 发明授权

US5495440A Semiconductor memory device having hierarchical bit line structure 失效
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US5495440A
公开(公告)日：1996-02-27
申请号：US321711
申请日：1994-10-12
申请人： Mikio Asakura
发明人： Mikio Asakura
IPC分类号： G11C11/401 , G11C11/404 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24
CPC分类号： G11C11/4097
摘要： A memory cell array is divided into a plurality of memory cell groups in the column direction. In each memory cell group, a sub-bit line SBL and a sub-cell plate line SCPL are located. A pair of main bit lines are arranged for memory cells on one column. For each sub-cell plate line, a switching transistor is provided connecting the sub-cell plate line to one main bit line in response to a group select signal. For each sub-bit line, a switching transistor is provided connecting corresponding sub-bit lines to the other main bit line in response to a group select signal BS. A constant voltage VBL is transmitted to the sub-cell plate line through a switching transistor rendered conductive in response to a group select signal CPPR. A dynamic type semiconductor memory device is provided whose memory array layout is facilitated and in which a sufficient read potential difference is produced on a pair of bit lines upon word line selection.
摘要翻译：存储单元阵列在列方向上分为多个存储单元组。在每个存储单元组中，定位有子位线SBL和子单元板线SCPL。一列主位线用于一列上的存储单元。对于每个子电池板线，提供响应于组选择信号将子电池板线连接到一个主位线的开关晶体管。对于每个子位线，提供响应于组选择信号BS将对应的子位线连接到另一个主位线的开关晶体管。恒定电压VBL通过响应于组选择信号CPPR而导通的开关晶体管传送到子电池板线。提供一种动态型半导体存储器件，其存储阵列布局方便，并且在字线选择时在一对位线上产生足够的读电位差。

62. 发明授权

US4953164A Cache memory system having error correcting circuit 失效
标题翻译：具有纠错电路的高速缓冲存储器系统
公开(公告)号：US4953164A
公开(公告)日：1990-08-28
申请号：US254233
申请日：1988-10-06
申请人： Mikio Asakura , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Mikio Asakura , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： G11C11/413 , G06F11/10 , G06F12/08 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1064 , G06F12/0802
摘要： There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell array. An error correcting circuit, a check bit generating circuit and a register are connected between the first memory cell array and the second memory cell array. Data which is frequently accessed is transferred from the first memory cell array to the second memory cell array and stored therein. Access is made to the second memory cell array. When data which is required is not in the second memory cell array, access is made to the first memory cell array. At the time of transferring data from the first memory cell array to the second memory cell array, errors are corrected by the error correcting circuit. The check bit generating circuit is responsive to data whose error is corrected by the error correcting circuit for generating new check bits.
摘要翻译：提供了第一存储单元阵列和第二存储单元阵列。第一存储单元阵列包括动态RAM，第二存储单元阵列包括静态RAM。此外，第二存储单元阵列具有比第一存储单元阵列小的容量。纠错电路，校验位产生电路和寄存器连接在第一存储单元阵列和第二存储单元阵列之间。频繁访问的数据从第一存储单元阵列传送到第二存储单元阵列并存储在其中。访问第二个存储单元阵列。当所需的数据不在第二存储单元阵列中时，对第一存储单元阵列进行访问。在将数据从第一存储单元阵列传送到第二存储单元阵列时，错误校正电路校正错误。校验位产生电路响应于错误被纠错电路校正的数据，用于产生新的校验位。

63. 发明授权

US4914632A Semiconductor devices having redundancy circuitry and operating method therefor 失效
标题翻译：具有冗余电路的半导体器件及其操作方法
公开(公告)号：US4914632A
公开(公告)日：1990-04-03
申请号：US271492
申请日：1988-11-15
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/804 , G11C29/808 , G11C29/781
摘要： A plurality of word drivers are provided corresponding to a plurality of word lines. A switch band is provided between the plurality of word drivers and a plurality of row decoders. Each row decoder is connected to four word drivers through the switch band. The state of connection between each of the row decoders and the word driver can be changed by the switch band. A spare row decoder, four word drivers and four spare word lines are provided. Any of the row decoders can be replaced with the spare row decoder. Consequently, four spare word driver and four spare word lines can be selected instead of the four word drivers and four word lines connected to the row decoder.
摘要翻译：针对多个字线提供多个字驱动器。在多个字驱动器和多个行解码器之间提供开关带。每行解码器通过开关带连接到四个字驱动器。每个行解码器和字驱动器之间的连接状态可以通过开关带来改变。提供备用行解码器，四个字驱动器和四个备用字线。任何行解码器都可以用备用行解码器替代。因此，可以选择四个备用字驱动器和四个备用字线，而不是四个字驱动器和连接到行解码器的四个字线。

64. 发明授权

US06762967B2 Semiconductor memory device having a circuit for fast operation 有权
标题翻译：具有用于快速操作的电路的半导体存储器件
公开(公告)号：US06762967B2
公开(公告)日：2004-07-13
申请号：US10443775
申请日：2003-05-23
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译：半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。

65. 发明授权

US06330173B1 Semiconductor integrated circuit comprising step-up voltage generation circuit 失效
标题翻译：包括升压电压产生电路的半导体集成电路
公开(公告)号：US06330173B1
公开(公告)日：2001-12-11
申请号：US09556442
申请日：2000-04-24
申请人： Kyoji Yamasaki , Mikio Asakura
发明人： Kyoji Yamasaki , Mikio Asakura
IPC分类号： H02M318
CPC分类号： H02M3/073 , G05F1/465 , G11C5/145 , G11C11/4074
摘要： A VPP generation circuit included in the inventive semiconductor integrated circuit includes a VPP dividing circuit dividing a step-up voltage VPP, a VDDA dividing circuit dividing an array voltage VDDA supplied to a memory cell array area, a VREFD generation circuit generating a reference voltage VREFD on the basis of an output of the VDDA dividing circuit and a comparator part comparing the reference voltage VREFD with a voltage VPPn output from the VPP dividing circuit. Thus, the step-up voltage VPP can be changed in response to change of the array voltage VDDA.
摘要翻译：包括在本发明的半导体集成电路中的VPP生成电路包括分压升压电压VPP的VPP分压电路，分配提供给存储单元阵列区域的阵列电压VDDA的VDDA分压电路，产生参考电压VREFD的VREFD生成电路基于VDDA分频电路的输出，以及将参考电压VREFD与从VPP分频电路输出的电压VPPn进行比较的比较部。因此，可以响应于阵列电压VDDA的变化而改变升压电压VPP。

66. 发明授权

US06295238B1 Semiconductor memory device having a circuit for fast operation 有权
标题翻译：具有用于快速操作的电路的半导体存储器件
公开(公告)号：US06295238B1
公开(公告)日：2001-09-25
申请号：US09604007
申请日：2000-06-26
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译：半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。

67. 发明授权

US6064607A Semiconductor memory device with predecoder 有权
标题翻译：具有预解码器的半导体存储器件
公开(公告)号：US6064607A
公开(公告)日：2000-05-16
申请号：US177484
申请日：1998-10-23
申请人： Takeo Miki , Mikio Asakura , Satoshi Kawasaki
发明人： Takeo Miki , Mikio Asakura , Satoshi Kawasaki
IPC分类号： G11C8/10 , G11C29/00 , G11C7/00
CPC分类号： G11C29/80 , G11C8/10
摘要： Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.
摘要翻译：第一和第二编程电路中的每一个包括确定节点，第一至第四保险丝，第一至第四N沟道MOS晶体管和第一至第四电源线。第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。因此，可以减少行地址预解码信号线的互连电容。此外，可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸，以允许整个芯片的布局面积较小。

68. 发明授权

US6061808A Semiconductor memory device having a multibit test mode 有权
标题翻译：具有多位测试模式的半导体存储器件
公开(公告)号：US6061808A
公开(公告)日：2000-05-09
申请号：US332364
申请日：1999-06-14
申请人： Tadaaki Yamauchi , Mikio Asakura , Takashi Ito
发明人： Tadaaki Yamauchi , Mikio Asakura , Takashi Ito
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C29/34 , G01R31/28 , G06F11/00
CPC分类号： G11C29/34
摘要： In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.
摘要翻译：在预定的多位测试模式中，多位测试电路114将确定结果数据对RDM0和/ RDM0发送到RDM3和/ RDM3，每个RDM3和/ RDM3对应于从由一列选择线选择的存储器单元读取的数据的逻辑的匹配/不匹配相应的一个存储单元平面块。在每个存储单元平面块中，由单个列选择行选择的存储单元列可以被替换为单元。根据确定结果数据RDM0和/ RDM0至RDM3和/ RDM3来替换包含有缺陷存储单元的存储单元列的单位。

69. 发明授权

US5859799A Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels 失效
标题翻译：半导体存储器件包括内部电源电路，其产生不同电平的多个内部电源电压
公开(公告)号：US5859799A
公开(公告)日：1999-01-12
申请号：US975151
申请日：1997-11-20
申请人： Yasuhiro Matsumoto , Mikio Asakura , Kouji Tanaka , Kyoji Yamasaki
发明人： Yasuhiro Matsumoto , Mikio Asakura , Kouji Tanaka , Kyoji Yamasaki
IPC分类号： G11C11/413 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4096 , G11C5/14 , G11C5/147
摘要： A plurality of internal power supply voltage generating circuits generate internal power supply voltages. A column select signal at the same voltage level as a first internal power supply voltage applied to a sense amplifier is generated to an I/O gate circuit connecting a bit line pair and an internal data line pair together. A current driving capability of an I/O gate circuit is made relatively small, so that rapid change in potential on a sense node of a sense amplifier is prevented. Thereby, inversion of latched data of the sense amplifier due to collision of data is prevented in such a case voltages on the internal data line pair are not equalized sufficiently.
摘要翻译：多个内部电源电压产生电路产生内部电源电压。与施加到读出放大器的第一内部电源电压相同的电压电平的列选择信号被产生到连接位线对和内部数据线对的I / O门电路。 I / O门电路的电流驱动能力相对较小，从而防止了读出放大器的感测节点上的电位的快速变化。因此，在这种情况下，防止了数据冲突导致的读出放大器的锁存数据的反转，内部数据线对上的电压不能充分均衡。

70. 发明授权

US5588130A Semiconductor memory device for simple cache system 失效
公开(公告)号：US5588130A
公开(公告)日：1996-12-24
申请号：US283367
申请日：1994-08-01
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G06F12/08 , G11C7/10 , G06F13/00 , G11C15/00
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

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