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61. 发明授权

US06421279B1 Flash memory control method and apparatus processing system therewith 有权
标题翻译：闪存控制方法和装置处理系统
公开(公告)号：US06421279B1
公开(公告)日：2002-07-16
申请号：US09927493
申请日：2001-08-13
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G11C800
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.
摘要翻译：半导体文件系统具有电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制器和控制部分，其控制控制器，其中对应于从外部系统指定的逻辑地址的物理地址是访问。第一非易失性存储器存储用于执行操作的外部系统的数据，指示物理和逻辑地址之间的对应关系的第一管理信息以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器先前存储接口信息。控制器确定物理扇区地址。控制部分用于控制来自/外部系统的数据的输入/输出，并用于从易失性存储器中的外部系统暂时将写数据存储到第一非易失性存储器中，然后将写入数据从易失性存储器传送到第一非易失性存储器记忆。

62. 发明授权

US06339519B1 Magnetic head device 失效
标题翻译：磁头装置
公开(公告)号：US06339519B1
公开(公告)日：2002-01-15
申请号：US09437680
申请日：1999-11-10
申请人： Izumi Nomura , Haruyuki Morita , Masashi Shiraishi , Mitsuyoshi Kawai , Takeshi Wada
发明人： Izumi Nomura , Haruyuki Morita , Masashi Shiraishi , Mitsuyoshi Kawai , Takeshi Wada
IPC分类号： G11B560
CPC分类号： G11B5/4853 , G11B5/486
摘要： There is disclosed a magnetic head device in which a head IC chip may be located relatively closer to a magnetic head and a thermal effect may be controlled to be within a range of acceptable degree. Said magnetic head device comprises a head slider having a magnetic head, a suspension member which is made of thin resilient material and supports the head slider at one end thereof, and a head IC chip, wherein the suspension member is attached to other member at the other end thereof. The IC chip is mounted on the suspension member. When the IC chip is selected to have appropriate disc side area and is mounted on the suspension member, the temperature of the IC chip itself may be maintained within a range of acceptable degree and that of the magnetic head may be also kept to be lower. When the electric power consumption of the IC chip is equal to or less than 410 mW, the disc side area thereof should be equal to or more than 1.1 mm2. The IC chip is mounted on a surface of the suspension member at a side facing to the disc at a position where a relative linear velocity equal to or more than 25 m/sec is generated with respect to said disc.
摘要翻译：公开了一种磁头装置，其中头部IC芯片可以相对靠近磁头定位，并且可以将热效应控制在可接受的程度的范围内。所述磁头装置包括具有磁头的磁头滑动器，由薄弹性材料制成的悬架构件，并在其一端支撑磁头滑块，以及磁头IC芯片，其中所述悬挂构件在所述磁头滑块的另一端。 IC芯片安装在悬挂构件上。当IC芯片被选择为具有适当的盘侧面积并安装在悬挂构件上时，IC芯片本身的温度可以保持在可接受的程度的范围内，并且磁头的温度也可以保持较低。当IC芯片的电力消耗等于或小于410mW时，其盘侧面积应等于或大于1.1mm 2。 IC芯片在相对于所述盘产生相对线速度等于或大于25m / sec的位置处，在面对盘的一侧安装在悬挂构件的表面上。

63. 发明授权

US06317294B1 Slider with negative and multiple positive pressure generation portions and head including the same 有权
标题翻译：具有负和多个正压力产生部分的滑块以及包括其的头部
公开(公告)号：US06317294B1
公开(公告)日：2001-11-13
申请号：US09649030
申请日：2000-08-28
申请人： Yoshimitsu Wada , Tetsuya Roppongi , Takeshi Wada , Isamu Sato
发明人： Yoshimitsu Wada , Tetsuya Roppongi , Takeshi Wada , Isamu Sato
IPC分类号： G11B560
CPC分类号： G11B5/6005
摘要： The present invention is directed to a slider, a head, a head device and a read/write apparatus that are extremely effective for achieving high density writing and an increase in the storage capacity. The slider comprises a front flat surface, a first positive pressure generating portion, a second positive pressure generating portion and a first negative pressure generating portion. The front flat surface, which is provided starting at a leading edge, ends at an intermediate point along a lengthwise direction. The first and second positive pressure generating portions have flat surfaces which are essentially of equal heights and are positioned separated from each other over a distance at two sides in a widthwise direction running perpendicular to a lengthwise direction, with edges at one end located toward the leading edge forming step faces rising up from the front flat surface in a step. The first negative pressure generating portion is provided behind the front flat surface relative to the airflow direction and has a base surface with a height which is lower than the height of the front flat surface.
摘要翻译：本发明涉及对于实现高密度写入和增加存储容量非常有效的滑块，头，头装置和读/写装置。滑块包括前平面，第一正压第二正压力产生部分和第一负压产生部分。从前缘开始设置的前平面在长度方向的中间点处终止。第一和第二正压力产生部分具有基本上相同的高度的平坦表面，并且在垂直于长度方向的宽度方向上的两侧彼此隔开一段距离定位，一端的边缘朝向前端边缘形成步骤在一个步骤中从前平坦表面起升。第一负压产生部分相对于气流方向设置在前平坦表面的后面，并且具有高度低于前平坦表面的高度的基面。

64. 发明授权

US6078520A Flash memory control method and information processing system therewith 有权
标题翻译：闪存控制方法和信息处理系统
公开(公告)号：US6078520A
公开(公告)日：2000-06-20
申请号：US357931
申请日：1999-07-21
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G06F11/14 , G06F12/08 , G11C29/00 , G11C17/00
CPC分类号： G11C29/765 , G06F11/1433 , G06F12/08 , G06F12/0802 , G06F12/0866 , G11C29/789 , G11C29/82 , G06F2212/2022 , G06F2212/312
摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
摘要翻译：当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由访问一个外部系统。第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。控制器具有控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，用于存储确定的物理扇区地址的装置，以及用于在由所述物理扇区地址确定的扇区中连续生成地址的装置。

65. 发明授权

US6054125A Purified mite allergen 失效
标题翻译：净化螨过敏原
公开(公告)号：US6054125A
公开(公告)日：2000-04-25
申请号：US9835
申请日：1998-01-20
申请人： Satoru Oka , Kazuhisa Ono , Seiko Shigeta , Takeshi Wada
发明人： Satoru Oka , Kazuhisa Ono , Seiko Shigeta , Takeshi Wada
IPC分类号： A61K39/35 , A61K38/00 , A61K49/00 , A61P37/08 , C07K14/00 , C07K14/435 , G01N33/48 , G01N33/53 , A61K39/00 , A61K39/36 , A61K39/38
CPC分类号： C07K14/43531 , A61K38/00
摘要： The present invention is directed to novel purified and isolated mite allergens possessing mite allergen activity with a molecular weight of about 94,000, about 40,000, about 16,000 or about 14,000 as determined by SDS-PAGE, which can be isolated from extracts of mites, and to a process for producing such mites allergens. The purified and isolated mite allergens of the present invention are useful as a pharmaceutical and a diagnostic composition for mite allergic diseases.
摘要翻译：本发明涉及具有螨过敏原活性的新型纯化和分离的螨变应原，其分子量约为94,000，约40,000，约16,000或约14,000，通过SDS-PAGE测定，其可以从螨的提取物中分离，并且一种生产这种螨变应原的方法。本发明的纯化和分离的螨过敏原可用作螨过敏性疾病的药物和诊断组合物。

66. 发明授权

US5917752A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5917752A
公开(公告)日：1999-06-29
申请号：US457761
申请日：1995-06-01
申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
发明人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3445 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/344 , G11C2216/20
摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

67. 外观设计

USD407327S Watchcase 失效
公开(公告)号：USD407327S
公开(公告)日：1999-03-30
申请号：US80402
申请日：1997-12-08
申请人： Takeshi Wada , Juhei Ozawa
设计人： Takeshi Wada , Juhei Ozawa

68. 外观设计

USD404654S Watchcase 失效
公开(公告)号：USD404654S
公开(公告)日：1999-01-26
申请号：US080021
申请日：1997-11-26
申请人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami
设计人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami

69. 外观设计

USD391498S Watchcase 失效
公开(公告)号：USD391498S
公开(公告)日：1998-03-03
申请号：US64399
申请日：1996-12-30
申请人： Toshiaki Kume , Takeshi Wada
设计人： Toshiaki Kume , Takeshi Wada

70. 发明授权

US5544098A Semiconductor memory device having an automatically activated verify function capability 失效
公开(公告)号：US5544098A
公开(公告)日：1996-08-06
申请号：US455152
申请日：1995-05-31
申请人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
发明人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/46 , G11C29/48 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/46 , G11C29/48
摘要： A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

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