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61. 发明申请

US20100228453A1 VEHICLE CONTROL SYSTEM DESIGNED TO MINIMIZE ACCELERATION SHOCK 有权
标题翻译：设计用于最小化加速冲击的车辆控制系统
公开(公告)号：US20100228453A1
公开(公告)日：2010-09-09
申请号：US12713989
申请日：2010-02-26
申请人： Tatsuya Saito
发明人： Tatsuya Saito
IPC分类号： G06F19/00 , B60W10/10 , B60W30/18
CPC分类号： F02D17/04 , B60W10/02 , B60W10/06 , B60W30/192 , B60W2510/1015 , B60W2520/10 , B60W2710/022 , B60W2710/025 , F02D29/02 , Y02T10/48 , Y10T477/26 , Y10T477/638 , Y10T477/6403 , Y10T477/6422
摘要： A vehicle control system for an engine-powered vehicle equipped with an engine and an automatic transmission with a clutch. When a given engine stop requirement is met during running of the engine, the system stops the engine automatically. When a given engine restart requirement is met after stop of the engine, the system restarts the engine and enters a clutch control mode to bring the clutch in the automatic transmission into a slippable state in which the clutch is permitted to slip based on the speed of the vehicle, thereby absorbing the acceleration shock which usually occurs upon engagement of the clutch to transmit engine torque to wheels of the vehicle when the engine is restarted, and the speed of the vehicle is relatively low.
摘要翻译：一种用于配备发动机和具有离合器的自动变速器的发动机动力车辆的车辆控制系统。当在发动机运行期间满足给定的发动机停止要求时，系统将自动停止发动机。当在发动机停止后满足给定的发动机重启要求时，系统重新启动发动机并进入离合器控制模式，以将离合器置于自动变速器中，使离合器允许滑动的滑动状态基于从而吸收当发动机重新启动时通常在离合器接合时将发动机扭矩传递到车辆的车轮时发生的加速冲击，并且车辆的速度相对较低。

62. 发明授权

US07774667B2 Semiconductor device and data processing system 失效
标题翻译：半导体器件和数据处理系统
公开(公告)号：US07774667B2
公开(公告)日：2010-08-10
申请号：US12054366
申请日：2008-03-24
申请人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
发明人： Tatsuya Saito , Kaname Yamasaki , Iwao Suzuki , Takeshi Bingo , Keiichi Horie
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/1201 , G11C2029/3602
摘要： The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.
摘要翻译：能够访问外部存储器的电路的测试设计成本降低。包括内置自检电路，用于独立于存储器控制器测试外部存储器，用于响应于能够耦合到存储器接口的外部存储器的访问请求执行存储器控制，以及TAP控制器用于控制内置自检电路并参考测试结果。采用多路复用器，根据外部通过TAP控制器输入的控制信息，可选择存储控制器或内置自检电路作为耦合到存储器接口的电路。内置的自检电路可编程地根据通过TAP控制器输入的指令产生和输出用于存储器测试的模式，并且将从外部存储器读取的数据与预期值进行比较。

63. 发明授权

US07714644B2 Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US07714644B2
公开(公告)日：2010-05-11
申请号：US12166666
申请日：2008-07-02
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F1/26 , H03F1/34 , H03F3/45085 , H03F3/45183 , H03F3/45968 , H03F2200/372 , H03F2200/375 , H03F2203/45534
摘要： An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
摘要翻译：提供放大器电路块和补偿电路块。放大器电路块包括用于从输入信号中减去补偿电路块的输出信号的模拟加法器和在宽带中工作的放大器电路。补偿电路块包括在低频区域具有低失调电压和低噪声的放大器电路，用于从放大器电路的输出信号中减去放大器电路的输出信号并产生其差分信号的模拟加法器块以及用于将差分信号负反馈给模拟加法器的反馈电路块。放大器电路块可以通过差分信号的负反馈来减小偏移电压和低带噪声，同时整个放大器电路的工作频带可以由放大器电路的特性决定。

64. 发明申请

US20100024239A1 DRUM-TYPE WASHER/DRYER 失效
标题翻译：鼓式洗衣机/干衣机
公开(公告)号：US20100024239A1
公开(公告)日：2010-02-04
申请号：US12094937
申请日：2006-10-17
申请人： Tetsuyuki Kono , Tatsuya Saito , Tatsuo Ioku , Satoru Nishiwaki
发明人： Tetsuyuki Kono , Tatsuya Saito , Tatsuo Ioku , Satoru Nishiwaki
IPC分类号： F26B21/00 , D06F58/04
CPC分类号： D06F25/00 , D06F58/20 , D06F58/206 , D06F58/24
摘要： A drum-type washer/dryer having an evaporator (34) for performing dehumidification by cooling air drawn from the inner space of a drum (24) and also having condenser (35) for heating the air dehumidified by the evaporator (34), wherein the air heated by the condenser (35) is made to sequentially pass through a duct (40) and a blowhole (47) and blown as dry air to clothes in the drum (24). A backflow preventing portion (52) is provided in the duct (40), and when bubbles flow back into the duct (40) from the inner space of the drum (24) through the blowhole (47), the backflow preventing portion (52) functions as resistance for preventing the back flow of the bubbles.
摘要翻译：一种具有蒸发器（34）的滚筒式洗衣机/干燥机，用于通过冷却从滚筒（24）的内部空间抽取的空气并且还具有用于加热由蒸发器（34）除湿的空气的冷凝器（35）来进行除湿，使由冷凝器（35）加热的空气依次通过管道（40）和气孔（47），并且作为干燥空气吹送到滚筒（24）中的衣服。在所述导管（40）中设置有防回流部（52），当从所述鼓（24）的内部空间经由所述气孔（47）流回到所述导管（40）内时，所述防回流部）作为防止气泡回流的阻力。

65. 发明申请

US20100013528A1 SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US20100013528A1
公开(公告)日：2010-01-21
申请号：US12504319
申请日：2009-07-16
申请人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H03L5/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
摘要翻译：半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的与其他操作相比，在电源系统中流动的电流。控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形在预定时段内的大电流操作。

66. 发明申请

US20090158087A1 SEMICONDUCTOR INTEGRATED CIRCUIT WITH MEMORY REPAIR CIRCUIT 审中-公开
标题翻译：具有存储器维修电路的半导体集成电路
公开(公告)号：US20090158087A1
公开(公告)日：2009-06-18
申请号：US12332915
申请日：2008-12-11
申请人： Hideshi Maeno , Wataru Uchida , Michinobu Nakao , Tatsuya Saito , Mitsuo Serizawa
发明人： Hideshi Maeno , Wataru Uchida , Michinobu Nakao , Tatsuya Saito , Mitsuo Serizawa
IPC分类号： G11C29/08 , G06F11/14 , G06F11/26
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/802
摘要： A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.
摘要翻译：提供了可以对RAM等中的至少一个存储电路进行修复的半导体集成电路，并且可以促进集成度的提高。编码电路3接收故障位数据失败[0] -fail [7]，对这8位故障位数据失败[7：0]进行编码，并输出4位（压缩位数）编码数据ef [ 3：0]。该编码数据ef [3：0]可以指示关于RAM1的各种故障信息。捕获电路4锁存满足预定锁存条件的编码数据ef [3：0]作为锁存数据cf [3：0]。捕获电路4可以执行锁存数据cf [3：0]的串行移位操作，并且可以串行输出作为串行数据输出So的锁存数据cf [3：0]。

67. 发明申请

US20080290495A1 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US20080290495A1
公开(公告)日：2008-11-27
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/528
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

68. 发明申请

US20080000410A1 Combination meter 有权
标题翻译：组合仪表
公开(公告)号：US20080000410A1
公开(公告)日：2008-01-03
申请号：US11806892
申请日：2007-06-05
申请人： Kouji Mori , Masahiko Mio , Tatsuya Saito
发明人： Kouji Mori , Masahiko Mio , Tatsuya Saito
IPC分类号： G01D7/04 , G01D13/02 , G01P5/00
CPC分类号： B60K37/02 , B60K2350/1064 , B60K2350/203 , G01D11/28 , G01D13/265 , G12B11/02 , Y10S116/06
摘要： The present invention is to provide a combination meter having a close arrangement of a plurality of drive axles of pointers so as to save a space thereof and provide a good design thereof. The combination meter includes a speedometer and a tachometer. A speedometer dial and a tachometer dial are disposed on the circumference of one circle. The pointers each include a deadweight holder to hold a deadweight. The deadweight holders are separately overlapped each other in directions of the drive axles. One of the drive axles is disposed on the center of the circle and the other is disposed close to the center.
摘要翻译：本发明提供一种组合仪表，其具有多个指针驱动轴的紧密布置，以便节省其空间并提供其良好的设计。组合仪表包括一个速度计和一个转速表。一个圆周的圆周上设有一个速度表刻度盘和一个转速表。指针每个都包括一个自重的持有人来保持自重。自重保持器在驱动轴的方向上分开重叠。驱动轴中的一个设置在圆的中心，另一个靠近中心设置。

69. 发明授权

US07277643B2 Clock extracting fabric in a communication device 失效
标题翻译：在通信设备中的时钟提取结构
公开(公告)号：US07277643B2
公开(公告)日：2007-10-02
申请号：US10629755
申请日：2003-07-30
申请人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
发明人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
IPC分类号： H04B10/00 , H04L27/00 , H04L12/50 , H04J3/06
CPC分类号： H04L25/14 , H04L7/033
摘要： A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.
摘要翻译：一种时钟再现系统的信号通信装置，其中从每个并行数据信号中提取时钟信号，以对每个数据信号进行重新排序。该装置包括一个参考时钟信号产生电路，它包括一个时钟提取电路，用于从接收的数据信号的多个比特中提取一个时钟信号;以及时钟信号选择电路，用于选择所提取的时钟信号之一。或者，参考时钟信号发生电路可以包括用于选择多个接收数据信号中的一个的数据信号选择电路和用于从所选位提取时钟信号的时钟提取电路。基于所得到的参考时钟信号，获得相位调整的时钟信号，以对接收到的数据信号的每一位进行重新编码。在选择电路中进行的选择是基于检测提取的时钟信号的频率异常的发生的时钟信号监视电路的输出而被切换的。因此，在提取时钟的位的异常的情况下，可以使用其他位继续提取时钟。

70. 发明申请

US20060082422A1 Connection structure of high frequency lines and optical transmission module using the connection structure 审中-公开
标题翻译：高频线连接结构和光传输模块采用连接结构
公开(公告)号：US20060082422A1
公开(公告)日：2006-04-20
申请号：US11240455
申请日：2005-10-03
申请人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
发明人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
IPC分类号： H03H7/38
CPC分类号： H01P5/08
摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
摘要翻译：应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。第一传输线的端面基本上被连接到接地导体的导体层覆盖。连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

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