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61. 发明申请

US20100316831A1 INFORMATION RECORDING AND REPRODUCING DEVICE 审中-公开
标题翻译：信息记录和复制设备
公开(公告)号：US20100316831A1
公开(公告)日：2010-12-16
申请号：US12859911
申请日：2010-08-20
申请人： Kohichi Kubo , Chikayoshi Kamata , Takayuki Tsukamoto , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
发明人： Kohichi Kubo , Chikayoshi Kamata , Takayuki Tsukamoto , Shinya Aoki , Takahiro Hirai , Toshiro Hiraoka
IPC分类号： B32B3/02
CPC分类号： G11B9/04
摘要： According to one embodiment, an information recording and reproducing device includes a resistive layer directly or indirectly added to a recording layer and having electric resistivity larger than electric resistivity in the low-resistance state of the recording layer. A first compound contained in the recording layer comprises a composite compound includes two or more kinds of cationic elements, at least one of the two or more kinds of cationic elements is a transition element having a d orbit filled incompletely with electrons, a shortest distance between cationic elements adjacent to each other is 0.32 nm or less.
摘要翻译：根据一个实施例，信息记录和再现装置包括直接或间接添加到记录层的电阻层，其电阻率大于记录层的低电阻状态下的电阻率。包含在记录层中的第一化合物包括复合化合物，包括两种或更多种阳离子元素，两种或多种阳离子元素中的至少一种是具有电子不完全填充轨道的过渡元素，阳离子彼此相邻的元素为0.32nm以下。

62. 发明授权

US07294382B2 Phase-change optical recording medium 失效
标题翻译：相变光记录介质
公开(公告)号：US07294382B2
公开(公告)日：2007-11-13
申请号：US11453854
申请日：2006-06-16
申请人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara
发明人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara
IPC分类号： B32B3/02
CPC分类号： G11B7/252 , G11B7/24038 , G11B7/243 , G11B7/2437 , G11B7/2534 , G11B7/257 , G11B7/2578 , G11B7/259 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , G11B2007/2571 , G11B2007/25711 , G11B2007/25715 , Y10T428/21
摘要： A phase-change optical recording medium has a phase-change recording film to which recording and erasure can be reversibly performed by irradiation with light, and at least one dielectric film formed of a SiOC film containing Si, O and C, and having a carbon concentration within a range of between 0.1 and 30 atomic %.
摘要翻译：相变型光记录介质具有通过照射可逆地进行记录和擦除的相变记录膜，以及至少一个由含有Si，O和C的SiOC膜形成的电介质膜，并且具有碳浓度在0.1至30原子％的范围内。

63. 发明申请

US20060269719A1 Phase-change optical recording medium 失效
公开(公告)号：US20060269719A1
公开(公告)日：2006-11-30
申请号：US11453855
申请日：2006-06-16
申请人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara
发明人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara
IPC分类号： B32B3/02
CPC分类号： G11B7/252 , G11B7/24038 , G11B7/243 , G11B7/2437 , G11B7/2534 , G11B7/257 , G11B7/2578 , G11B7/259 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , G11B2007/2571 , G11B2007/25711 , G11B2007/25715 , Y10T428/21
摘要： A phase-change optical recording medium has a phase-change recording film to which recording and erasure can be reversibly performed by irradiation with light, and at least one dielectric film formed of a SiOC film containing Si, O and C, and having a carbon concentration within a range of between 0.1 and 30 atomic %.

64. 发明申请

US20050106353A1 Phase-change optical recording medium 失效
标题翻译：相变光记录介质
公开(公告)号：US20050106353A1
公开(公告)日：2005-05-19
申请号：US10976367
申请日：2004-10-29
申请人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara , Urara Ichihara
发明人： Tsukasa Nakai , Sumio Ashida , Keiichiro Yusu , Takayuki Tsukamoto , Noritake Oomachi , Naomasa Nakamura , Katsutaro Ichihara , Urara Ichihara
IPC分类号： G11B7/254 , B32B3/02 , G11B7/24 , G11B7/243 , G11B7/257
CPC分类号： G11B7/2433 , G11B7/252 , G11B7/2534 , G11B7/259 , G11B2007/24308 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , G11B2007/25706 , G11B2007/2571 , G11B2007/25711 , G11B2007/25713 , G11B2007/25715 , Y10T428/21
摘要： A phase-change optical recording medium has a first information layer including a phase-change optical recording film arranged in a position close to the light incident side, a second information layer including another phase-change optical-recording film arranged in a position remote from the light incident side and an interlayer separating film arranged between the first information layer and the second information layer, in which at least one of the first information layer and the second information layer includes a noise reduction film in contact with the interlayer separating film. The noise reduction film is formed of SiOx (1≦x≦2) or SiOC.
摘要翻译：相变光记录介质具有包括布置在靠近光入射侧的相变光记录膜的第一信息层，第二信息层，包括布置在远离光入射侧的位置的另一相变光记录膜光入射侧和布置在第一信息层和第二信息层之间的层间隔离膜，其中第一信息层和第二信息层中的至少一个包括与层间隔离膜接触的降噪膜。降噪膜由SiOx（1 <= x <= 2）或SiOC形成。

65. 发明授权

US06353309B1 Switching circuit having a switching semiconductor device and control method thereof 失效
标题翻译：具有开关半导体器件的开关电路及其控制方法
公开(公告)号：US06353309B1
公开(公告)日：2002-03-05
申请号：US09608023
申请日：2000-06-29
申请人： Mitsuaki Ootani , Yoshiyuki Wasada , Nobuyuki Yamazaki , Yasushi Inoue , Takeshi Nakayama , Junichi Shimamura , Yuji Ebinuma , Takayuki Tsukamoto
发明人： Mitsuaki Ootani , Yoshiyuki Wasada , Nobuyuki Yamazaki , Yasushi Inoue , Takeshi Nakayama , Junichi Shimamura , Yuji Ebinuma , Takayuki Tsukamoto
IPC分类号： G05F140
CPC分类号： G05F1/575 , H03K17/122
摘要： The present invention provides a switching circuit and an electronic switching component having a switching semiconductor device to perform switching between a conducting state and a non-conducting state of a conducting path to thereby reduce the power loss thereof and a control method thereof. In the present invention, at least two FETs 11 and 12, wherein the FET 11 has a faster switching time and the FET 12 has a lower ON resistance. Active terminals (drains and sources) of the FETs 11 and 12 are connected to each other in parallel. By employing these FETs 11 and 12, the conversion between an ON-state and an OFF-state of the conducting path is performed. In converting from the non-conducting state to the conducting state, the control circuit 13 first turns on the FET 11 and then turns on the FET 12 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof. In converting from the conducting state to the non-conducting state, the control circuit 13 first turns off the FET 12 and then turns off the FET 11 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof.
摘要翻译：本发明提供一种开关电路和具有开关半导体器件的电子开关元件，以进行导通路径的导通状态和非导通状态之间的切换，从而降低其功率损耗及其控制方法。在本发明中，至少两个FET 11和12，其中FET 11具有更快的开关时间，并且FET 12具有较低的导通电阻。 FET 11和12的有源端子（漏极和源极）并联连接。通过采用这些FET11,12，进行导通路径的导通状态和截止状态之间的转换。在从非导通状态转换为导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先接通FET 11，然后导通FET 12。在从导通状态转换为非导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先关断FET 12，然后关断FET 11。

66. 发明授权

US09076525B2 Semiconductor storage device and method of controlling data thereof 有权
标题翻译：半导体存储装置及其数据的控制方法
公开(公告)号：US09076525B2
公开(公告)日：2015-07-07
申请号：US13597773
申请日：2012-08-29
申请人： Mizuki Kaneko , Tomonori Kurosawa , Yoichi Minemura , Hiroshi Kanno , Takafumi Shimotori , Takayuki Tsukamoto
发明人： Mizuki Kaneko , Tomonori Kurosawa , Yoichi Minemura , Hiroshi Kanno , Takafumi Shimotori , Takayuki Tsukamoto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/72
摘要： A semiconductor storage device includes a memory cell array, and a control circuit. The memory cell array has memory cells including variable resistive elements disposed at intersections of a plurality of first lines and a plurality of second lines. The control circuit performs a set pulse applying operation, and a cure pulse applying operation. The set pulse applying operation applies a set pulse to a variable resistive element so as to cause the variable resistive element to transition from a high resistance state to a low resistance state. The cure pulse applying operation applies a cure pulse to the variable resistive element. The cure pulse has a polarity that is opposite of a polarity of the set pulse, and is larger than the set pulse.
摘要翻译：半导体存储装置包括存储单元阵列和控制电路。存储单元阵列具有包括设置在多个第一线和多条第二线的交叉处的可变电阻元件的存储单元。控制电路执行设定脉冲施加操作和固化脉冲施加操作。设置脉冲施加操作将设定脉冲施加到可变电阻元件，以使可变电阻元件从高电阻状态转变到低电阻状态。固化脉冲施加操作对可变电阻元件施加固化脉冲。固化脉冲具有与设定脉冲的极性相反的极性，并且大于设定脉冲。

67. 发明授权

US08861265B2 Semiconductor storage device and data control method thereof 有权
标题翻译：半导体存储装置及其数据控制方法
公开(公告)号：US08861265B2
公开(公告)日：2014-10-14
申请号：US13597814
申请日：2012-08-29
申请人： Tomonori Kurosawa , Mizuki Kaneko , Takafumi Shimotori , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno
发明人： Tomonori Kurosawa , Mizuki Kaneko , Takafumi Shimotori , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2013/0083 , G11C2213/72
摘要： In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.
摘要翻译：在存储单元阵列中，包括可变电阻元件的存储单元布置在多个第一布线和多个第二布线之间的交叉部分处。控制电路执行设定操作，复位操作和训练操作。在设定动作中，向可变电阻元件施加设定脉冲，将可变电阻元件从高电阻状态变为低电阻状态。在复位操作中，将具有与设定脉冲的极性相反的极性的复位脉冲施加到可变电阻元件，以将可变电阻元件从低电阻状态改变为高电阻状态。在训练操作中，将设定脉冲和复位脉冲连续施加到可变电阻元件。

68. 发明授权

US08804402B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08804402B2
公开(公告)日：2014-08-12
申请号：US13722210
申请日：2012-12-20
申请人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa
发明人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0007 , G11C13/0069 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括设置在多个第一线和多条第二线的每个交点处的多个存储单元; 以及控制电路，将所选择的第一线电压施加到所选择的第一线，相对于相邻未选择的第一线大于所选择的第一线电压的相邻未选择的第一线电压，以及大于相邻的未选择的第一线电压的未选择的第一线电压将未选择的第一线电压提供给未选择的第一线，以及将选择的第二线电压大于所选择的第一线电压至选定的第二线，以及将小于所选择的第二线电压的未选择的第二线电压施加到未选择的第二线电压线。

69. 发明授权

US08698228B2 Non-volatile memory device and method for manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08698228B2
公开(公告)日：2014-04-15
申请号：US12886202
申请日：2010-09-20
申请人： Takeshi Araki , Takeshi Yamaguchi , Mariko Hayashi , Kohichi Kubo , Takayuki Tsukamoto
发明人： Takeshi Araki , Takeshi Yamaguchi , Mariko Hayashi , Kohichi Kubo , Takayuki Tsukamoto
IPC分类号： H01L29/792
CPC分类号： H01L27/101 , B82Y10/00 , G11B5/743 , G11B9/04 , G11B9/1472 , G11B9/149 , G11C11/22 , G11C13/0007 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1625 , H01L45/1675
摘要： According to one embodiment, a non-volatile memory device includes a stacked structure and a voltage application portion. The stacked structure includes a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion. The voltage application portion applies a voltage to the memory portion to cause a change in a resistance in the memory portion to store information. The surface includes a first region and a second region. The first region contains at least one of a metallic element, Si, Ga, and As. The first region is conductive. The second region contains at least one of the metallic element, Si, Ga, and As, and has a content ratio of nonmetallic element higher than a content ratio of nonmetallic element in the first region. At least one of the first region and the second region has an anisotropic shape on the surface.
摘要翻译：根据一个实施例，非易失性存储器件包括堆叠结构和电压施加部分。堆叠结构包括存储部分和与存储器部分堆叠并具有面向存储部分的部分的表面的电极。电压施加部分向存储器部分施加电压以引起存储器部分中的电阻的变化以存储信息。表面包括第一区域和第二区域。第一区域包含金属元素Si，Ga和As中的至少一种。第一个区域是导电的。第二区域包含金属元素Si，Ga和As中的至少一种，并且具有高于第一区域中的非金属元素的含量比的非金属元素的含量比。第一区域和第二区域中的至少一个在表面上具有各向异性的形状。

70. 发明授权

US08665634B2 Semiconductor memory device 有权
公开(公告)号：US08665634B2
公开(公告)日：2014-03-04
申请号：US13600448
申请日：2012-08-31
申请人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa
发明人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/0002 , G11C11/1673 , G11C11/419 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

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