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61. 发明授权

US06992392B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06992392B2
公开(公告)日：2006-01-31
申请号：US10227189
申请日：2002-08-23
申请人： Katsumi Mori
发明人： Katsumi Mori
IPC分类号： H01L23/48
CPC分类号： H01L23/5329 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 100 includes wiring layers 12 disposed in a specified pattern on a base 10, and an interlayer dielectric layer 20 that covers the wiring layers 12. The interlayer dielectric layer 20 includes a stress relieving dielectric layer 22 disposed in a specified pattern on the base 10, and a planarization dielectric layer 26 that covers the wiring layers 12 and the stress relieving dielectric layers 22, and is formed from a liquid dielectric member. The interlayer dielectric layer 20 may further include a base dielectric layer 24 and a cap dielectric layer 28.
摘要翻译：半导体装置100包括以特定图案设置在基底10上的布线层12和覆盖布线层12的层间电介质层20。层间电介质层20包括在基板10上以规定图案设置的应力消除介电层22和覆盖布线层12和应力消除电介质层22的平坦化介电层26，并由液体电介质构件。层间电介质层20还可以包括基极电介质层24和盖电介质层28。

62. 发明授权

US06888250B2 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
标题翻译：半导体装置及其制造方法，掩模数据生成方法，掩模和计算机可读记录介质
公开(公告)号：US06888250B2
公开(公告)日：2005-05-03
申请号：US09809635
申请日：2001-03-15
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/48
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过的方向延伸的第一虚拟线性线L 1 行方向。行方向和第一虚拟线性线L 1限定为2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L 1上的方式设置。半导体器件还限定列垂直于行方向的方向，以及沿着列方向的方向延伸的第二假想直线L 2。列方向和第二虚拟线性线L 2限定为2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L 2上的方式设置。

63. 发明申请

US20050073052A1 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium 有权
标题翻译：半导体装置及其制造方法，掩模数据生成方法，掩模和计算机可读记录介质
公开(公告)号：US20050073052A1
公开(公告)日：2005-04-07
申请号：US10999290
申请日：2004-11-29
申请人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
发明人： Katsumi Mori , Kei Kawahara , Yoshikazu Kasuya
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522 , H01L23/528 , H01L29/40
CPC分类号： H01L27/0207 , G06F17/5077 , G06F17/5081 , H01L21/76816 , H01L21/76819 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
摘要翻译：半导体器件具有设置在与第一布线层30相同的层上的第一布线层30和多个伪布线层32.半导体器件限定行方向，并且沿着穿过第一布线层30的方向延伸的第一虚拟线性线L1 行方向。行方向和第一虚拟线性线L1限定2-40度的角度，并且虚设布线层32以位于第一虚拟线性线L1上的方式设置。半导体器件还限定垂直于行方向的列方向，以及在沿着列方向的方向上延伸的第二虚拟线性线L2。列方向和第二虚拟线性线L2限定2-40度的角度，并且虚设布线层32以位于第二虚拟线性线L2上的方式设置。

64. 发明授权

US06876015B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US06876015B2
公开(公告)日：2005-04-05
申请号：US10202063
申请日：2002-07-25
申请人： Katsumi Mori
发明人： Katsumi Mori
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include a fuse section 110 in which a plurality of fuses 20 to be fused by irradiation of a laser beam are formed. The fuses 20 are arranged at a pitch X, and an insulation layer 36 having a specified film thickness covers upper portions of the fuses 20. The fuses 20 may have a width W and a film thickness T that have a relation indicated by the following equation: T≧0.4/W. Furthermore, the width W of the fuse 20 may be 3 μm or less, and may be less than ½ of the pitch X of the fuses 20. Also, the film thickness of the fuse 20 may be 0.7 μm or less.
摘要翻译：半导体器件可以包括熔丝部分110，其中形成通过激光束的照射熔化的多个保险丝20。保险丝20以间距X布置，并且具有指定膜厚度的绝缘层36覆盖保险丝20的上部。保险丝20可以具有宽度W和膜厚度T，该宽度W和膜厚度T具有下列等式：T> = 0.4 / W。此外，保险丝20的宽度W可以为3μm以下，并且可以小于保险丝20的间距X的1/2。另外，保险丝20的膜厚可以为0.7μm以下。

65. 发明授权

US06852489B2 Simple and quick method for determining the nucleotide sequence of a mitochondrial 21S ribosomal RNA gene of yeast belonging to Saccharomyces cerevisiae 失效
标题翻译：用于确定属于酿酒酵母的酵母的线粒体21S核糖体RNA基因的核苷酸序列的简单且快速的方法
公开(公告)号：US06852489B2
公开(公告)日：2005-02-08
申请号：US09796348
申请日：2001-03-02
申请人： Katsumi Mori , Takuma Gamou
发明人： Katsumi Mori , Takuma Gamou
IPC分类号： C12N15/09 , C12Q1/04 , C12Q1/68 , C07H21/04 , C12P19/34
CPC分类号： C12Q1/6895
摘要： The present invention provides a simple and quick method for determining the nucleotide sequence of the mitochondrial 21S ribosomal RNA gene of Saccharomyces cerevisiae by gene amplification technique, and a method for classifying Saccharomyces cerevisiae strains using the same nucleotide sequence. To achieve this object, the mitochondrial 21S ribosomal RNA gene of Saccharomyces cerevisiae is amplified by gene amplification technique, thereby determining the nucleotide sequence of the gene.
摘要翻译：本发明提供了一种用于通过基因扩增技术测定酿酒酵母的线粒体21S核糖体RNA基因的核苷酸序列的简单且快速的方法，以及使用相同核苷酸序列对酿酒酵母菌株进行分类的方法。为了达到此目的，通过基因扩增技术扩增酿酒酵母的线粒体21S核糖体RNA基因，从而确定该基因的核苷酸序列。

66. 发明授权

US06794082B2 Alkaline battery 有权
标题翻译：碱性电池
公开(公告)号：US06794082B2
公开(公告)日：2004-09-21
申请号：US09947978
申请日：2001-09-06
申请人： Katsumi Mori , Takumi Ohhara , Kenji Sato
发明人： Katsumi Mori , Takumi Ohhara , Kenji Sato
IPC分类号： H01M208
CPC分类号： H01M2/0275 , H01M2/0222 , H01M2/0272 , H01M4/48 , H01M4/62 , H01M6/12 , H01M10/52 , H01M2004/028 , H01M2300/0014
摘要： An alkaline battery constructed of a cathode can and an anode cup in such a way that an open end of the cathode can is sealed by the anode cup, with a gasket interposed between them, characterized in that the open end of the anode cup is folded back in U-shape along its periphery and the fold is tightened for hermetic sealing by the internal periphery of the open end of the cathode can, with the gasket interposed between them, the anode cup has a higher hydrogen over potential material coating layer formed in a limited region on the inside thereof excluding the bottom of the U-shaped fold and the outer periphery of the fold, the cathode can contains the cathode active material and silver-nickelite (AgNiO2), the anode cup contains the anode mix which is mercury-free zinc or zinc alloy powder as the anode active material.
摘要翻译：一种由阴极罐和阳极杯构成的碱性电池，使得阴极罐的开口端由阳极杯密封，垫圈介于它们之间，其特征在于阳极杯的开口端折叠沿着其周边回U形，并且折叠部被紧固以通过阴极罐的开口端的内周进行气密密封，其中衬垫介于它们之间，阳极杯具有较高的在潜在材料涂层上形成的氢除了U形折叠的底部和折叠的外周之外的其内部的有限区域，阴极可以包含正极活性物质和银 - 镍铋（AgNiO 2），阳极杯包含作为汞的阳极混合物 - 无锌或锌合金粉末作为阳极活性材料。

67. 发明授权

US06560765B2 Method for generating mask data, mask and computer readable recording media 有权
标题翻译：用于生成掩码数据，掩码和计算机可读记录介质的方法
公开(公告)号：US06560765B2
公开(公告)日：2003-05-06
申请号：US09808098
申请日：2001-03-14
申请人： Katsumi Mori , Yoshikazu Kasuya , Kei Kawahara
发明人： Katsumi Mori , Yoshikazu Kasuya , Kei Kawahara
IPC分类号： G06F1750
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restriction region pattern 262 that defines a restriction region 40 in a semiconductor substrate, (b) setting dummy patterns 310 that define dummy convex regions 32, and (c) mixing the restriction region pattern 262 and the dummy patterns 310, wherein the dummy patterns 310 that at least partially overlap the restriction region pattern 262 are entirely excluded.
摘要翻译：提供了一种用于产生用于在半导体器件中的沟槽隔离区域中以指定图案形成伪凸区的掩模数据的方法。还提供了掩模和计算机可读记录介质。该方法包括以下步骤：（a）在半导体衬底中设置限定区域40的限制区域图案262，（b）设置限定伪凸区域32的虚拟图案310，以及（c）将限制区域图案262 并且伪图案310，其中至少部分地与限制区域图案262重叠的虚拟图案310被完全排除。

68. 发明授权

US06518633B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06518633B2
公开(公告)日：2003-02-11
申请号：US09773779
申请日：2001-02-02
申请人： Katsumi Mori , Kenji Kojima
发明人： Katsumi Mori , Kenji Kojima
IPC分类号： H01L2976
CPC分类号： H01L21/76229
摘要： A semiconductor wafer 10 has a chip region 20 and a non-chip region 22. Dummy trench isolation regions 40 are formed in at least a part of the non-chip region 22 of the semiconductor wafer 10. The dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22. A method is also provided for processing a semiconductor wafer 10 having a chip region 20 and a non-chip region 22. The method includes a process for forming trench isolation regions in the semiconductor wafer 10. The process includes the steps of forming dummy trench isolation regions 40 in at least a part of the non-chip region 22 of the semiconductor wafer 10, wherein the dummy trench isolation regions 40 are formed in a region extending by a specified distance D10 into the non-chip region 22 from a boundary between the chip region 20 and the non-chip region 22.
摘要翻译：半导体晶片10具有芯片区域20和非芯片区域22.在半导体晶片10的非芯片区域22的至少一部分中形成虚设沟槽隔离区域40.形成虚设沟槽隔离区域40 在从芯片区域20和非芯片区域22之间的边界延伸指定距离D10的区域到非芯片区域22中。还提供了一种用于处理具有芯片区域20和非芯片区域22.该方法包括在半导体晶片10中形成沟槽隔离区域的工艺。该工艺包括在半导体晶片的非芯片区域22的至少一部分中形成虚设沟槽隔离区域40的步骤如图10所示，其中虚设沟槽隔离区40形成在从芯片区域20和非芯片区域22之间的边界延伸到非芯片区域22的特定距离D10的区域中。

69. 发明授权

US06475879B2 Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device 有权
标题翻译：半导体晶片，其加工方法以及制造半导体器件的方法
公开(公告)号：US06475879B2
公开(公告)日：2002-11-05
申请号：US09761958
申请日：2001-01-17
申请人： Katsumi Mori
发明人： Katsumi Mori
IPC分类号： H01L2146
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
摘要翻译：提供了一种用于处理具有芯片形成芯片区域的半导体晶片和不正常形成芯片的非芯片区域的方法。该方法包括以下步骤：在半导体晶片中形成沟槽隔离区，并在半导体晶片的非芯片区域的至少一部分中形成虚设沟槽隔离区。

70. 发明授权

US5625637A Surface emitting semiconductor laser and its manufacturing process 失效
标题翻译：表面发射半导体激光器及其制造工艺
公开(公告)号：US5625637A
公开(公告)日：1997-04-29
申请号：US359964
申请日：1994-12-19
申请人： Katsumi Mori , Tatsuya Asaka , Hideaki Iwano
发明人： Katsumi Mori , Tatsuya Asaka , Hideaki Iwano
IPC分类号： H01S5/028 , H01S5/183 , H01S5/22 , H01S3/19
CPC分类号： H01S5/18369 , H01S2304/04 , H01S5/18308 , H01S5/18341 , H01S5/2211 , H01S5/2224
摘要： A surface emitting semiconductor laser, with a resonator cavity transverse to the planar extent of the deposited layers, is provided with a first reflection mirror on the substrate side composed of alternating layers comprising a first layer that is made of a Group III-V compound semiconductor and a second layer that is made of a Group III-V compound semiconductor with an energy bandgap that is larger than that of the first layer. A second reflection mirror is provided at the opposite end of the cavity adjacent to a column like resonator portion. At least the first reflection mirror comprises a distributive Bragg reflection (DBR) multiple layer mirror that has an interface region between first and second layers having a carrier concentration that is higher than that of other regions. The column like resonator portion is surrounded by a buried layer which may consist of two layers, the first layer functioning as barrier layer and the second layer functioning as a flattening layer. The first layer may be comprised of a silicon compound and the second layer may be comprised of SOG or a resin compound. The multiple layer band structure of the DBR mirror is improved, current easily flows vertically through the multiple layers and the element resistance is low. In addition, a simple and reliable method is employed to fabricate the DBR mirror and the dual buried layer, respectively, because the doping concentration is controlled through dopant gas flow control or is controlled through light and can be easily accomplished without using comparatively high temperature processing.
摘要翻译：具有横向于沉积层的平面范围的谐振腔的表面发射半导体激光器在基板侧上设置有由交替层组成的第一反射镜，该交替层包括由III-V族化合物半导体以及由具有比第一层的能带隙大的能带隙的III-V族化合物半导体制成的第二层。第二反射镜设置在与柱状谐振器部分相邻的腔的相对端。至少第一反射镜包括分布布拉格反射（DBR）多层反射镜，其在第一和第二层之间具有高于其它区域的载流子浓度的界面区域。柱状谐振器部分被埋入层包围，该掩埋层可以由两层组成，第一层用作阻挡层，第二层用作平坦化层。第一层可以由硅化合物组成，第二层可以由SOG或树脂化合物构成。 DBR镜的多层带结构得到改善，电流容易垂直流过多层，元件电阻较低。另外，采用简单可靠的方法来制造DBR镜和双埋层，因为掺杂浓度通过掺杂剂气体流量控制来控制或通过光控制并且可以容易地实现而不使用比较高的温度处理。

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