专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20080149932A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080149932A1
公开(公告)日：2008-06-26
申请号：US11946606
申请日：2007-11-28
申请人： Katsuaki Natori , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Masayuki Tanaka , Kazuaki Nakajima , Yoshio Ozawa , Akihito Yamamoto
发明人： Katsuaki Natori , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Masayuki Tanaka , Kazuaki Nakajima , Yoshio Ozawa , Akihito Yamamoto
IPC分类号： H01L27/115
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/513 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜，设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极，的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

62. 发明申请

US20080012061A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080012061A1
公开(公告)日：2008-01-17
申请号：US11687758
申请日：2007-03-19
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译：非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。第一和第二存储单元的浮置栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

63. 发明授权

US07195930B2 Cleaning method for use in an apparatus for manufacturing a semiconductor device 有权
标题翻译：用于制造半导体器件的设备的清洁方法
公开(公告)号：US07195930B2
公开(公告)日：2007-03-27
申请号：US11204079
申请日：2005-08-16
申请人： Takashi Shimizu , Akihito Yamamoto
发明人： Takashi Shimizu , Akihito Yamamoto
IPC分类号： H01L21/00
CPC分类号： C23C16/455 , C23C16/4405 , C23C16/52
摘要： A cleaning method for use in an apparatus for manufacturing a semiconductor device includes: measuring components and concentration of each component of gas in a process chamber of an apparatus for manufacturing a semiconductor device, or selected from a group including gas in the chamber, a process gas in a gas inlet pipe, and gas in a gas outlet pipe; performing a prescribed process on a substrate in the chamber, while adjusting the components and the concentration of each component of the process gas, and of an atmosphere in the chamber, on the basis of the values measured, and taking the substrate from the chamber after the process is subjected; and generating and applying a cleaning gas on the basis of the values measured, the cleaning gas having such components and such concentration as to remove residues.
摘要翻译：一种用于制造半导体器件的设备的清洁方法，包括：测量半导体器件制造装置的处理室中的气体成分和浓度，或者选自包括室中的气体的组中的气体成分和浓度，进气管中的气体和气体出口管中的气体; 在室内的基板上进行规定的处理，同时基于所测量的值调节处理气体的各成分和室内的气氛的成分和浓度，并从室后取出基板该过程受到影响基于所测量的值产生和施加清洁气体，具有这种组分的清洁气体和除去残留物的浓度。

64. 发明申请

US20070026149A1 Semiconductor manufacturing apparatus and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体制造装置及半导体装置的制造方法
公开(公告)号：US20070026149A1
公开(公告)日：2007-02-01
申请号：US11494735
申请日：2006-07-28
申请人： Takashi Shimizu , Kazuo Saki , Kazuhiro Nishiki , Akihito Yamamoto , Shinji Mori
发明人： Takashi Shimizu , Kazuo Saki , Kazuhiro Nishiki , Akihito Yamamoto , Shinji Mori
IPC分类号： C23C16/00
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/3144 , H01L22/20
摘要： In a process of annealing an insulating film such as a silicon oxide film (SiO2) or a silicon oxynitride film (SiON) provided in a processing chamber 6 within an atmosphere of an inert gas 2 guided from a first mass flow controller 3 via a gas inlet 7, an amount of SiO sublimated from the surface of the insulating film in the processing chamber 6 is measured by a mass spectrometer 10, and an amount of oxygen gas 4 guided to the processing chamber 6 from a second mass flow controller 5 is controlled by a controller 1 so that the SiO concentration does not exceed a predetermined level, thereby effectively controlling the SiO sublimation. As a result, the film deterioration caused by the SiO sublimation is prevented and an insulating film having a high reliability and good characteristics can be formed in a controllable manner.
摘要翻译：在将惰性气体2的气氛2中引导的处理室6中设置的氧化硅膜（SiO 2/2）或氧氮化硅膜（SiON）等绝缘膜退火的工序中，通过气体入口7的第一质量流量控制器3，通过质谱仪10测量从处理室6中的绝缘膜的表面升华的SiO的量，并且从处理室6中引导到处理室6的量的氧气第二质量流量控制器5由控制器1控制，使得SiO浓度不超过预定水平，从而有效地控制SiO升华。结果，防止了由SiO升华引起的膜劣化，并且可以以可控的方式形成具有高可靠性和良好特性的绝缘膜。

65. 发明申请

US20060046441A1 Method of monitoring selectivity of selective film growth method, and semiconductor device fabrication method 审中-公开
标题翻译：监测选择性薄膜生长方法选择性的方法和半导体器件制造方法
公开(公告)号：US20060046441A1
公开(公告)日：2006-03-02
申请号：US11211745
申请日：2005-08-26
申请人： Kiyotaka Miyano , Akihito Yamamoto , Yoshihiko Saito
发明人： Kiyotaka Miyano , Akihito Yamamoto , Yoshihiko Saito
IPC分类号： H01L21/20
CPC分类号： H01L29/7834 , C30B25/16 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/66628
摘要： According to the present invention, there is provided a selectivity monitoring method in a selective film growth method of selectively growing a film in a predetermined region on a semiconductor substrate, comprising: selectively growing the film on a surface of the semiconductor substrate while measuring temperature of the surface of the semiconductor substrate by at least one pyrometer placed in a non-contact state above the surface of the semiconductor substrate; and determining that selectivity of the growth of the film has decreased, when the temperature changes from a predetermined value or changes from a predetermined angle in a graph showing change of the temperature during film formation.
摘要翻译：根据本发明，提供了选择性膜生长方法中选择性地生长半导体衬底上预定区域中的膜的选择性监测方法，包括：在半导体衬底的表面上选择性地生长膜，同时测量温度所述半导体衬底的表面通过在所述半导体衬底的表面上方处于非接触状态的至少一个高温计; 并且当温度从预定值变化或者在显示成膜期间温度变化的曲线图中从预定角度改变时，确定膜生长的选择性已经降低。

66. 发明授权

US5750436A Thermal processing method and apparatus therefor 失效
公开(公告)号：US5750436A
公开(公告)日：1998-05-12
申请号：US485506
申请日：1995-06-07
申请人： Kenichi Yamaga , Yuichi Mikata , Akihito Yamamoto
发明人： Kenichi Yamaga , Yuichi Mikata , Akihito Yamamoto
IPC分类号： C23C16/34 , C23C16/44 , C23C16/455 , C23C16/54 , C23C16/56 , H01L21/31 , H01L21/316
CPC分类号： C23C16/4409 , C23C16/345 , C23C16/455 , C23C16/54 , C23C16/56
摘要： An Si.sub.3 N.sub.4 layer is formed on a surface of a wafer, which is an object to be processed, at a high temperature of, for example, 780.degree. C., using a vertical thermal processing apparatus having a reaction tube of a double-wall structure comprising an inner tube and an outer tube in which a predetermined reduced-pressure status is maintained within the reaction tube while a reaction gas comprising, for example, SiH.sub.2 Cl.sub.2 and NH.sub.3 is made to flow from an inner side to an outer side of the inner tube by the action of a first gas supply pipe and first exhaust pipe provided in the thermal processing apparatus. Next, the temperature in the interior of the reaction tube is raised to, for example, 1000.degree. C., a reaction gas comprising, for example, H.sub.2 O vapor and HCl is made to flow from the outer side to the inner side of the inner tube by the action of a second gas supply pipe and second exhaust pipe, and an SiO.sub.2 layer is formed by the oxidation of the surface of the Si.sub.3 N.sub.4 layer formed on the surface of the wafer, under normal-pressure conditions. The use of a combined chamber enables the implementation of film formation and either oxidation or diffusion processing without having to remove the object to be processed from the reaction tube, and thus prevents the intrusion of a natural oxide layer or the incorporation of particles into a thin film structure of, for example, SiO.sub.2 and Si.sub.3 N.sub.4 layers used as a multi-layer insulating film for devices such as DRAMs.

67. 发明授权

US5502010A Method for heat treating a semiconductor substrate to reduce defects 失效
标题翻译：用于半导体衬底的热处理以减少缺陷的方法
公开(公告)号：US5502010A
公开(公告)日：1996-03-26
申请号：US91266
申请日：1993-07-15
申请人： Souichi Nadahara , Kikuo Yamabe , Hideyuki Kobayashi , Kunihiro Terasaka , Akihito Yamamoto , Naohiko Yasuhisa
发明人： Souichi Nadahara , Kikuo Yamabe , Hideyuki Kobayashi , Kunihiro Terasaka , Akihito Yamamoto , Naohiko Yasuhisa
IPC分类号： H01L21/223 , C30B33/00 , H01L21/322 , H01L21/324 , H01L21/477
CPC分类号： C30B29/06 , C30B33/00 , H01L21/3225 , Y10S438/909
摘要： A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a high temperature heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before the high temperature heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree. C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.
摘要翻译：一种处理半导体衬底的方法包括在气氛下对半导体衬底进行热处理的步骤。该方法包括在非氧化性气氛下，在不低于1100℃的温度下对半导体衬底进行高温热处理的步骤，其中在加热到半导体衬底的高温热处理之前的热处理被加热处理温度和热处理时间落入由连接（900℃，4分钟），（800℃，40分钟），（700℃，11小时）和（ 600℃，320小时），其中热处理温度绘制在横坐标上，热处理时间绘制在图的纵坐标上。

68. 发明授权

US08766373B2 Semiconductor memory and method of manufacturing the same 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US08766373B2
公开(公告)日：2014-07-01
申请号：US13185930
申请日：2011-07-19
申请人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
发明人： Masahiro Kiyotoshi , Akihito Yamamoto , Yoshio Ozawa , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L21/70
CPC分类号： H01L27/249 , H01L21/02532 , H01L21/02595 , H01L21/28282 , H01L21/30604 , H01L21/31055 , H01L21/3212 , H01L21/32136 , H01L21/762 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L29/513 , H01L29/518 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
摘要翻译：半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

69. 发明申请

US20130195991A1 Composition for Treatment of Damaged Part 审中-公开
标题翻译：治疗损伤部位的组成
公开(公告)号：US20130195991A1
公开(公告)日：2013-08-01
申请号：US13637107
申请日：2011-03-25
申请人： Minoru Ueda , Yoichi Yamada , Katsumi Ebisawa , Akihito Yamamoto , Kiyoshi Sakai , Kohki Matsubara , Hisashi Hattori , Masahiko Sugiyama , Takanori Inoue
发明人： Minoru Ueda , Yoichi Yamada , Katsumi Ebisawa , Akihito Yamamoto , Kiyoshi Sakai , Kohki Matsubara , Hisashi Hattori , Masahiko Sugiyama , Takanori Inoue
IPC分类号： A61K35/12
CPC分类号： A61K35/12 , A61K35/28 , A61K35/30 , A61K35/32 , A61K35/545 , A61K38/18 , A61K38/1833 , A61K38/1841 , A61K38/1858 , A61K38/1866 , A61K38/30 , C12N5/0664 , A61K2300/00
摘要： The present invention provides a damaged part treatment composition for repairing a damaged part of a target tissue that includes a stem cell-conditioned medium obtained by culturing stem cells; a damaged part treatment method for repairing or restoring a damaged part of a target tissue that includes administering the damaged part treatment composition to a patient having the target tissue for the damaged part treatment composition in an amount therapeutically effective for repairing the damaged part of the target tissue; a method of treating cerebral infarction that includes administering the damaged part treatment composition to a cerebral infarct patient in an amount effective for repairing a damaged part of the brain; and a method of treating a CNS disease that includes administering, as a CNS disease treatment composition, the damaged part treatment composition to a CNS disease patient in a therapeutically effective amount.
摘要翻译：本发明提供一种用于修复目标组织的损伤部分的损伤部分处理组合物，其包括通过培养干细胞获得的干细胞条件培养基; 用于修复或恢复目标组织的损伤部分的损坏部分处理方法，包括将损伤的部分处理组合物施用于具有损伤部分处理组合物的目标组织的患者，其量以治疗有效的量修复靶的损伤部分组织; 一种治疗脑梗死的方法，其包括以有效修复脑损伤部分的量将损伤的部分治疗组合物给予脑梗死患者; 以及治疗CNS疾病的方法，其包括以治疗有效量向CNS疾病患者施用所述损伤的部分治疗组合物作为CNS疾病治疗组合物。

70. 发明授权

US08110865B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08110865B2
公开(公告)日：2012-02-07
申请号：US12888140
申请日：2010-09-22
申请人： Masayuki Tanaka , Daisuke Nishida , Ryota Fujitsuka , Katsuyuki Sekine , Akihito Yamamoto , Katsuaki Natori , Yoshio Ozawa
发明人： Masayuki Tanaka , Daisuke Nishida , Ryota Fujitsuka , Katsuyuki Sekine , Akihito Yamamoto , Katsuaki Natori , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7883
摘要： A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极，所述第二绝缘膜包括下氮化硅膜，形成在所述下氮化硅膜上的下氧化硅膜，形成在所述下氧化硅膜上并含有金属元素的中间绝缘膜，所述中间绝缘膜具有相对电介质大于7的常数，形成在中间绝缘膜上的上部氧化硅膜和形成在上部氧化硅膜上的上部氮化硅膜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式