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    • 61. 发明授权
    • Multilayer circuit board and electronic device
    • 多层电路板和电子设备
    • US08217270B2
    • 2012-07-10
    • US11990860
    • 2006-08-18
    • Tadahiro OhmiAkinobu TeramotoAkihiro Morimoto
    • Tadahiro OhmiAkinobu TeramotoAkihiro Morimoto
    • H05K1/03
    • H05K1/024H05K3/4602H05K3/4626H05K3/4673H05K2201/0116H05K2201/0195H05K2201/0209H05K2201/0254
    • A multilayered circuit board which is provided with a low-permittivity interlayer insulating film, and which can significantly improve the performance such as signal transmission characteristics of the multilayered circuit board such as a package and a printed board, because the surface in contact with the interlayer insulating film of the circuit board has no unevenness to eliminate the lowering of production yield and the deterioration of high-frequency signal transmission characteristics; and electronic equipment using the circuit board. The multilayered circuit board comprises, mounted on a substrate, plural wiring layers and plural insulating layers positioned between the plural wiring layers, wherein at least part of the plural insulating layers are composed of a porous insulating layer containing at least any of materials selected from a porous material group consisting of porous material, aerogel, porous silica, porous polymer, hollow silica and hollow polymer, and a non-porous insulating layer formed on at least one surface of the porous insulating layer and not containing the porous material group.
    • 具有低介电常数层间绝缘膜的多层电路板,能够显着地提高诸如封装和印刷电路板的多层电路板的信号传输特性等性能,因为与中间层 电路板的绝缘膜没有不均匀性,消除了生产成本的降低和高频信号传输特性的恶化; 和使用电路板的电子设备。 多层电路板包括安装在基板上的多个布线层和位于多个布线层之间的多个绝缘层,其中多个绝缘层的至少一部分由多孔绝缘层组成,多孔绝缘层至少含有选自 由多孔材料,气凝胶,多孔二氧化硅,多孔聚合物,中空二氧化硅和中空聚合物组成的多孔材料组和形成在多孔绝缘层的至少一个表面上并且不包含多孔材料组的无孔绝缘层。
    • 67. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07863713B2
    • 2011-01-04
    • US12086886
    • 2006-12-20
    • Tadahiro OhmiAkinobu TeramotoKazufumi Watanabe
    • Tadahiro OhmiAkinobu TeramotoKazufumi Watanabe
    • H01L29/04
    • H01L27/1211H01L21/823807H01L21/823821H01L21/823878H01L29/045H01L29/785H01L2029/7857
    • For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.
    • 为了均衡CMOS电路中的上升和下降操作速度,由于它们之间的载流子迁移率的差异,需要使p型MOS晶体管和n型MOS晶体管的面积彼此不同。 该区域不平衡防止了半导体器件的集成度的提高。 NMOS晶体管和PMOS晶体管各自具有在(100)面和(110)面上具有沟道区的三维结构,使得两个晶体管的沟道区和栅绝缘膜的面积等于 其他。 因此,可以使栅极绝缘膜等的面积相等并且使栅极电容彼此相等。 此外,基板上的积分度可以提高到常规技术的两倍。
    • 69. 发明申请
    • Method of Chemical Mechanical Polishing
    • 化学机械抛光方法
    • US20100240283A1
    • 2010-09-23
    • US12567092
    • 2009-09-25
    • Takenao NemotoTadahiro OhmiAkinobu TeramotoXun GuAra PhilipossianYasa Sampurno
    • Takenao NemotoTadahiro OhmiAkinobu TeramotoXun GuAra PhilipossianYasa Sampurno
    • B24B1/04
    • H01L21/3212B24B37/042
    • [Problem] To improve polishing efficiency while lowering shear force added to semiconductor wafers while increasing polishing speed, without damaging the wafer's processing surface or the membrane under it.[Solution Method] Pressing the revolving head or carrier 34 that holds fixed the semiconductor wafer 10 to the polishing pad or polishing cloth 30 attached to rotating polishing table 32 in this CMP device and while rotating carrier 34 and polishing table 32 respectively, and supplying liquid slurry to polishing pad 30 from nozzle 36, planarization by chemical processes and mechanical processes is carried out by removing membranes of the lower face of semiconductor wafer 10 (the processing surface). The chemical mechanical polishing process of the present invention in regard to the size of the relationship between the rotation rate of semiconductor wafer 10 fW and the number of rotations of polishing pad 30 fP has 3 fp
    • [问题]为了提高抛光效率,同时降低加入到半导体晶片中的剪切力同时增加抛光速度,而不损坏晶片的处理表面或其下面的膜。 [解决方案方法]将固定有半导体晶片10的旋转头或载体34按压到分别安装在该CMP装置中的旋转研磨台32上的研磨垫或抛光布30,同时分别旋转载体34和研磨台32, 从喷嘴36到研磨垫30的浆料,通过化学处理和机械加工的平坦化,通过去除半导体晶片10的下表面(处理用面)的膜来进行。 本发明的化学机械研磨方法关于半导体晶片10f的旋转速度与抛光垫30fP的旋转速度之间的关系的大小作为其下限为3fp