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61. 发明专利

JPH11121720A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH11121720A
公开(公告)日：1999-04-30
申请号：JP28864497
申请日：1997-10-21
申请人： TOSHIBA CORP
发明人： SAKUI YASUSHI , IWATA YOSHIHISA
IPC分类号： H01L21/8247 , H01L21/76 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To prevent increase in the threshold voltage of transistor elements due to the miniaturization of the elements in a semiconductor device made of a plurality of the transistor elements on a semiconductor substrate. SOLUTION: P type impurity layers 14 having a higher concentration than that of a substrate 11 is formed directly below field oxide films 12, while N-type impurity layers 13 are formed so as to encircle these P type impurity layers 14. In such a constitution, the expansion of the P type impurity layers 14 on the peripheral part thereof is avoided so that the effects of transistor element on the threshold voltage and the threshold voltage on the substrate bias by the P type impurity layers 14 may be mitigated.

62. 发明专利

JPH10228788A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10228788A
公开(公告)日：1998-08-25
申请号：JP8767098
申请日：1998-03-31
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To perform quickly writing and erasing for a memory cells by comparing data read out from a memory cell with data held in a data latch means succeeding to writing operation, and performing batch verifying outputting finish of writing when it is discriminated that writing is performed for the memory cell. SOLUTION: After data of a memory cell is read out to a bit line, a selection gate and a control gate are reset at the time of writing verifying operation, a verifying signal ϕV is made 'H', and (Vcc-Vth) is outputted to only a bit line BLi in which '1' is written. After that, a signal ϕRP is made 'L', a signal ϕRN is made 'H', and rewriting data is latched. When all rewriting data is '1', a writing finish detecting signal VDTC is made 'H'. Writing verifying operations repeated until VDTC is made 'H', a detected result is outputted from a data input/output pin or a READY/BUSY pin.

63. 发明专利

JPH10228783A NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS OPERATION METHOD 失效
公开(公告)号：JPH10228783A
公开(公告)日：1998-08-25
申请号：JP2652297
申请日：1997-02-10
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： IWATA YOSHIHISA , YAMANE TOMOKO
IPC分类号： G11C16/02 , G11C16/06 , G11C29/00 , G11C29/04 , G11C29/50 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve a lifetime of a non-volatile semiconductor memory by performing weak writing, making only a memory cell having large movement in read-disturbe '0' cell, and discovering easily a memory cell having large movement. SOLUTION: A redundant circuit consisting of a second memory cell array 21 and a second row decoder 22 is used for replacing a memory cell with a redundant memory cell when a cell having large movement exists in read- disturb. Week page writing is performed with a shorter pulse than a writing pulse at the time of writing data so that a threshold value of a normal cell is smaller than read-out voltage at the time of reading data. At the time, As a writing speed of a cell having large movement in read-disturb is faster than that of a normal cell, it is made a '0' cell. Next, a cell having large movement can be easily discriminated by verifying whether a '0' cell exists or not.

64. 发明专利

JPH08315590A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH08315590A
公开(公告)日：1996-11-29
申请号：JP16233496
申请日：1996-06-03
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06
摘要： PURPOSE: To perform write/erase operation quickly for all objective memories by quickly detecting whether write/erase operation for a plurality of memory cells has been performed correctly or not. CONSTITUTION: A high voltage is applied to a P type region prior to writing operation and the data in memory cells is erased by setting a control gate at DV. A writing data is latched from IO,/IO into a data latch/sense amplifier, i.e., a CMOSFF, and a precharge signal ϕp goes to H to precharge a bit line BLi. The bit line BLi is provided with 0V when 0 is written while provided with an intermediate potential VM when 1 is written by the latched data. A write confirming operation is precharged, from a state where the bit line BLi is reset to 0V, to drive a select gate and a control gate thus reading the data in the memory cell onto the bit line BLi. Subsequently, a verify signal ϕV goes to H and the potential is outputted only from a bit line BLi used for writing 1 and the potential is sensed.

65. 发明专利

JPH05101662A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH05101662A
公开(公告)日：1993-04-23
申请号：JP25947091
申请日：1991-10-07
申请人： TOSHIBA CORP
发明人： MOMOTOMI MASAKI , ITO YASUO , IWATA YOSHIHISA , TANAKA TOMOHARU , TANAKA YOSHIYUKI
IPC分类号： G11C11/409 , G11C5/14 , G11C7/10 , G11C16/06 , G11C16/20 , G11C16/26
摘要： PURPOSE:To reduce the current consumption, to suppress the generation of noise, and to shorten the access time by setting the precharge voltage of a signal line to a specific low voltage value. CONSTITUTION:A precharge circuit 20 connected to a pair of data input/output lines IO is provided with MOS transistors TRs 23 and 24, and a control signal phiC is inputted to gates of both MOS TRs to turn on them at the time of precharging. Input/output lines IO are mutually connected with an equalizing MOS TR 22 between them. A precharge voltage HVCC is set to a half of the value obtained by subtracting the threshold voltage of the MOS TR from a supply voltage VCC. Thus, it is unnecessary to generate the precharge voltage BVCC at the time of amplifying and reading out the potential difference between 10 lines by an operational amplifier 21, and the current consumption is reduced, and the noise is reduced and the access time is shortened because the current consumption accompanied with charging/discharging of IO lines is small.

66. 发明专利

JPH04302898A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04302898A
公开(公告)日：1992-10-26
申请号：JP9146991
申请日：1991-03-29
申请人： TOSHIBA CORP
发明人： TANAKA YOSHIYUKI , TANAKA TOMOHARU , IWATA YOSHIHISA , SAKUI YASUSHI , MOMOTOMI MASAKI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To provide a semiconductor storage device which has a clock synchronizing type sense amplifier circuit enabling data read out with no malfunction. CONSTITUTION:A memory cell array 1 and a first and a second clock signal synchronizing type inverters 21 and 22, which read out bit line data, configure the clock synchronizing type sense amplifier circuit 2. During a data read out period, in the sense amplifier circuit 2, the first clock signal synchronizing type inverter 21, whose input terminals are connected to bit line BL, is first activated, its output data are defined then, the second clock signal synchronizing type inverter is activated.

67. 发明专利

JPH04254994A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04254994A
公开(公告)日：1992-09-10
申请号：JP1549891
申请日：1991-02-06
申请人： TOSHIBA CORP
发明人： ITO YASUO , TANAKA TOMOHARU , IWATA YOSHIHISA , SAKUI YASUSHI , MOMOTOMI MASAKI , TANAKA YOSHIYUKI , MASUOKA FUJIO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To provide a NAND cell type EEPROM which enables a high-speed data writing. CONSTITUTION:The high-speed data writing is attained by providing a bit line charging means 31 which charges a plural number of bit lines to an intermediate voltage in advance at the time of writing data and selectively discharging the pre-charged bit lines according to data to write in.

68. 发明专利

JPH0388200A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0388200A
公开(公告)日：1991-04-12
申请号：JP22542989
申请日：1989-08-31
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA , ITO YASUO , TANAKA TOMOHARU , OHIRA HIDEKO , MOMOTOMI MASAKI
IPC分类号： G11C17/00 , G11C8/10 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To realize a highly integrated EEPROM by making the best use of the advantage of a NAND cell by sharing the control gate driving circuit of a NAND cell type EEPROM with plural control gate lines. CONSTITUTION:The control gate driving circuit 13 is shared with the plural control gate lines CG11-CG48, and the output of the driving circuit is supplied to the control gate of the NAND cell selected via a transfer gate 12 controlled with the selection gate line of the NAND cell. Thereby, the high integration of the EEPROM can be attained as a whole without impairing the advantage to make a NAND cell array into high integration. Especially, by arranging the circuit 13 in the periphery of the cell array in a direction intersection orthogonally to that of the control gate line of the cell array, not in the extension there of, the layout of the circuit 13 can be performed in a state where the pitch of a gate line is sufficiently narrow.

69. 发明专利

JPH0373497A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0373497A
公开(公告)日：1991-03-28
申请号：JP23989689
申请日：1989-09-18
申请人： TOSHIBA CORP
发明人： ITO YASUO , MOMOTOMI MASAKI , IWATA YOSHIHISA , TANAKA TOMOHARU , MASUOKA FUJIO
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To optimize a word line boosting circuit part by providing the non- volatile semiconductor memory device with the 1st boosting circuits for supplying a high voltage to a selection gate line and the 2nd boosting circuits for supplying a high voltage to a word line controlled and selected by the 1st boosting circuit. CONSTITUTION:In a row decoder 12, output lines for selecting word lines WL are connected to word lines WL corresponding to plural cell blocks 111, 112 in common and the cell blocks 111, 112 are selected by output lines for selecting selection gate lines SG. Since a selection signal is supplied also to the other word line WL 112 or 111 when one block line 111 or 112 is selected, the output of the 1st boosting circuit 15 for supplying the high voltage to the selection gate line SG is executed with priority and the 2nd boosting circuit 16 for supply ing the high voltage to the word line WL is controlled by the output of the circuit 15. Thereby, even when the word line WL is selected, the word line WL in the non-selected cell block 111 or 112 can be prevented from being boosted.

70. 发明专利

JPH02130798A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02130798A
公开(公告)日：1990-05-18
申请号：JP28476388
申请日：1988-11-10
申请人： TOSHIBA CORP
发明人： ITO YASUO , MOMOTOMI MASAKI , IWATA YOSHIHISA , TANAKA TOMOHARU , MASUOKA FUJIO
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To assure a high-speed performance for the title memory device by utilizing an external power source for a bit line boosting circuit. CONSTITUTION:When an H level is supplied to a gate terminal N at the time of rewriting data, MOS transistors (TR) Q1 and Q2 are simultaneously turned on and charging is started to a bit line BL1. The voltage across the terminal N rises to the output high voltage VPP2 of an internal boosting circuit by the action of a bootstrap circuit after prescribed time. Therefore, when the threshold voltage Vth of the Tr Q1 is lower than about VPP2-VPP1=2V, the bit line BL1 is charged to the output voltage VPP1 of an external power source. Even when the threshold voltage Vth of the MOS Tr Q1 is >=2V, the voltage across the bit line BL1 rises to VPP2-Vth. In this case, when 20V is supplied to the gate signal SG1 of a selected gate S11 and 0V is supplied to the control gate signal line CG1 of a memory cell M11, the high potential at the bit line BL1 is almost transmitted to drains of memory cells M11,... and electrons are injected into a floating gate from a substrate. In the case the electrons in the floating gate of the cell M11 are discharged, the bit line BL1 is set to 0V by applying a high voltage across signals lines SG1 and CG1.

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